MAX11014_08 Datasheet, PDF (26/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
I²C Compatibility (SPI/I2C = DGND)
The MAX11014/MAX11015 communicate through an
I²C-compatible 2-wire serial interface consisting of a
serial data line (SDA) and a serial clock line (SCL). SDA
and SCL facilitate bidirectional communication between
the MAX11014/MAX11015 and the master at data rates
up to 3.4MHz. The master (typically a µC) initiates data
transfer on the bus and generates the SCL signal to per-
mit data transfer. The MAX11014/MAX11015 behave as
I²C slave devices that transfer and receive data.
SCL and SDA must be pulled high for proper I²C oper-
ation. This is typically done with pullup resistors (1kΩ or
greater). Series resistors are optional. The series resis-
tors protect the input architecture from high-voltage
spikes on the bus lines and minimize crosstalk and
undershoot of the bus signals.
One data bit transfers during each SCL clock cycle. A
minimum of 9 bytes is required to transfer a byte in or
out of the MAX11014/MAX11015 (8 bits and an
acknowledge (ACK)/not-acknowledge (NACK) bit).
Data is latched in on SCL’s rising edge and read out on
SCL’s falling edge. The data on SDA must remain sta-
ble during the high period of the SCL clock pulse.
Changes in SDA while SCL is stable and high are con-
sidered control signals (see the START and STOP
Conditions section). Both SDA and SCL remain high
when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high (Figure 11). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
High-Speed Mode section).
The address byte, command byte, and data bytes are
transmitted between the START and STOP conditions.
Nine clock cycles are required to transfer the data in or
out of the MAX11014/MAX11015. See Figures 15 and
16. If the receiver returns a not-acknowledge bit, the
MAX11014/MAX11015 releases the bus. If the not
acknowledge occurs in the middle of a 16-bit word, the
remaining bits are lost.
S
Sr
P
SDA
SCL
S = START.
Sr = REPEATED START.
P = STOP.
Figure 11. START and STOP Conditions
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