MAX11014_08 Datasheet, PDF (28/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
Transfer from F/S mode to HS mode by addressing all
devices on the bus with the HS-mode master code
0000 1XXX (X = don’t care). After successfully receiv-
ing the HS-mode master code, the MAX11014/
MAX11015 issue a NACK, allowing SDA to be pulled
high for one cycle.
After the NACK, the MAX11014/MAX11015 operate in
HS mode. Send a repeated START followed by a slave
address to initiate HS-mode communication. If the master
generates a STOP condition, the MAX11014/MAX11015
return to F/S mode. Use a repeated START condition in
place of a STOP condition to leave the bus active and the
mode unchanged.
Command Byte/Data Bytes (Write Cycle)
Begin a write cycle by issuing a START condition
(through the master), followed by 7 slave address bits
(Figure 13) and a write bit (R/W = 0). After writing the
8th bit, the MAX11014/MAX11015 (the slave) issue an
acknowledge signal by pulling SDA low for one clock.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 15 and
17, Table 1, and the Command Byte section. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
the command byte, write 2 data bytes, allowing for two
additional acknowledge signals after each byte. The
master ends the write cycle by issuing a STOP condition.
When operating in HS mode, a STOP condition returns
the bus to F/S mode. See the High-Speed Mode section.
The MAX11014/MAX11015’s internal conversion clock fre-
quency is 4.8MHz (typ), resulting in a typical conversion
time of 4.6µs. Figure 15 shows a complete write cycle.
HS-MODE MASTER CODE
S = START.
Sr = REPEATED START.
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
Figure 14. F/S-Mode to HS-Mode Transfer
F/S MODE
HS MODE
MASTER TO SLAVE
SLAVE TO MASTER
4-BYTE WRITE CYCLE
1
7
S
SLAVE
ADDRESS
11
8
1
A
A
W C COMMAND BYTE C
K
K
8
DATA BYTE
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS.
Figure 15. Write Cycle
1
8
A
C
DATA BYTE
K
S = START.
ACK = ACKNOWLEDGE.
P = STOP.
Sr = REPEATED START.
11
A
C P OR Sr
K
NUMBER OF BITS
28 ______________________________________________________________________________________