MAX11014_08 Datasheet, PDF (47/70 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 20. SHUT (Write)
BIT NAME
X
DATA BIT
D15–D12
FULLPD
D11
FBGON
D10
WDGPD
D9
OSCPD
D8
PD2-3
D7
PD2-2
D6
PD2-1
D5
PD2-0
D4
PD1-3
D3
PD1-2
D2
PD1-1
D1
PD1-0
D0
RESET STATE
X
1
0
FUNCTION
Don’t care.
Set to 1 to power down all internal blocks. FULLPD takes precedence
over any of the other power-down control bits. All commands in progress
are suspended and the DACs and ADC are disabled. The serial
interface remains functional. FULLPD is set to 1 on power-up. Set the
FULLPD bit to 0 after power-up and before writing any other commands
to activate all internal blocks.
Set to 1 to force the internal bandgap voltage block to power up, remain
powered up between conversions, and avoid the 50µs reference power-
up delay time. Forcing the internal reference to remain on increases the
power dissipation. Set FBGON to its default state of 0 to power the
bandgap voltage as required by the ADC.
Set to 1 to turn off the watchdog oscillator. The watchdog oscillator
0
monitors the internal ALU and resets the logic state to the startup
condition after 80ms. This reduces power consumption but prevents the
self-monitoring function of the watchdog timer.
0
Set to 1 to power down the internal oscillator. OSCPD is automatically
reset to 0 after receiving the next interface command.
1
Set to 1 to power down the channel 2 current-sense amplifier.
1
Set to 1 to power down the channel 2 gate-drive amplifier.
Set to 1 to power down the channel 2 DAC summing node
1
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
1
Set to 1 to power down the channel 2 DAC.
1
Set to 1 to power down the channel 1 current-sense amplifier.
1
Set to 1 to power down the channel 1 gate-drive amplifier.
Set to 1 to power down the channel 1 DAC summing node
1
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
1
Set to 1 to power down the channel 1 DAC.
Table 21. LDAC (Write)
BIT NAME
X
DATA BIT
D15–D2
DACCH2
D1
DACCH1
D0
RESET STATE
X
N/A
N/A
Don’t care.
FUNCTION
Set to 1 to load the channel 2 DAC output register with the value stored
in the channel 2 DAC input register.
Set to 1 to load the channel 1 DAC output register with the value stored
in the channel 1 DAC input register.
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