81080V Datasheet, PDF (9/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
Figure 6. Boundary Scan Register Circuit for I/O Pins
SCANIN
(from previous
cell)
BSCAN
Registers
DQ
DQ
HIGHZ
EXTEST
PROG_MODE
BSCAN
Latches
TOE
Normal
Function 0
DQ
OE ₁
EXTEST
PROG_MODE
DQ
Normal
Function
0
1
I/O Pin
DQ
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset*
*Internal power-up reset signal. Not connected to external reset pin.
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell
Shift DR
Clock DR
DQ
SCANOUT
(to next cell)
9