81080V Datasheet, PDF (6/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
Figure 3. ispLSI 8000V Macrocell Overview
Single PT
PTSA
PTSA Bypass
PT Clock
Global Clock Enable
Global Clock 0
Global Clock 1
Global Clock 2
PT Reset
GRST
PT Preset
Reset pin
GRST
Preset/Reset Input has Global Polarity Control
*Not available for Macrocells 9 and 10.
From PT80
DQ
Clk En
R/L
RP
Bus Input From Tristate
Bus Track*
Feedback to AND Array
To Big Fast Megablock
or Global Interconnect
To Specific
Global Tristate Bus*
From Macrocell
9 or 10
To All Macrocells and I/O Cells
: Function Selector (E² Cell Controlled)
6