81080V Datasheet, PDF (4/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
ispLSI 8000V Family Description (Continued) Embedded Tristate Bus
signals is selectable on an individual I/O cell basis. The
I/O cell register can be programmed to operate as a D-
type register or a D-type latch.
The input thresholds are fixed at levels which comply with
both 3.3V and 2.5V interfaces. The output driver can
source 4mA and sink 8mA (3.3V output supply). The
output drivers have a separate VCCIO power supply
which is independent of the main VCC supply for the
device. This feature allows the output drivers to run from
either 3.3V or 2.5V while the device logic is always
powered from 3.3V. The output drivers also provide
individually programmable edge rates and open drain
capability. A programmable pullup resistor is provided to
tie off unused inputs and a programmable bus-hold latch
is available to hold tristate outputs in their last valid state
until the bus is driven again by another device.
The ispLSI 8000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface using the JTAG protocol. Bound-
ary Scan test is also supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 81080V Description
The ispLSI 81080V device has nine Big Fast Megablocks
for a total of 9 x 120 = 1080 macrocells.
Each Big Fast Megablock has a total of 24 I/O cells and
the Global Routing Plane has a total of 144 I/O cells. This
gives (9 x 24) + 144 = 360 I/Os for the full I/O version,
while the partial I/O version contains 72 Big Fast
Megablock I/Os + 120 global I/Os = 192 I/Os.
There is a 108-line embedded internal tristate bus as part
of the Global Routing Plane (GRP), enabling multiple
GLBs to drive the same tracks. This bus can be parti-
tioned into various bus widths such as twelve 9-line
buses, six 18-line buses or three 36-line buses. The
GLBs can dynamically share a subset of the Global
Routing Plane tracks. This feature eliminates the need to
convert tristate buses to wide multiplexers on the pro-
grammable device. Up to 18 macrocells per GLB can
participate in driving the embedded tristate bus. The
remaining two macrocells per GLB are used to generate
the internal tristate driver control signals on each data
byte (with parity). The embedded tristate bus can also be
configured as an extension of an external tristate bus
using the bidirectional capability of the I/O cells con-
nected to the Global Routing Plane. The Global Routing
Plane I/Os 0-8 and 15-23 from each group (I/OGx as
defined in the I/O Pin Location Table) can connect to the
internal tristate bus as well as the unidirectional/non-
tristate global routing channels. I/Os 9-14 connect only to
the global routing channel.
The embedded tristate bus has internal bus hold and
arbitration features in order to make the function more
“user friendly”. The bus hold feature keeps the internal
bus at the previously driven logic state when the bus is
not driven to eliminate bus float. The bus arbitration is
performed on a “first come, first served” priority. In other
words, once a logic block drives the bus, other logic
blocks cannot drive the bus until the first releases the bus.
This arbitration feature prevents internal bus contention
when there is an overlap between two bus enable sig-
nals. Typically, it takes about 3ns to resolve one bus
signal coming off the bus to another bus signal driving the
bus. The arbitration feature, combined with the predict-
ability of the CPLD, makes the embedded tristate bus the
most practical for real world bus implementation.
The total registers in the device is the sum of macrocells
plus I/O cells, 1080 + 360 = 1440 registers.
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