81080V Datasheet, PDF (14/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
External Switching Characteristics¹
Over Recommended Operating Conditions
PARA- TEST
METER COND.⁴
#²
DESCRIPTION
-125
-90
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Prop Delay, BFM Input to Same BFM Output, 4 PT Bypass — 8.5 — 10.0 — 15.0 ns
tpd2
A 2 Prop Delay, Global Input to Global Output
— 14.5 — 16.0 — 24.0 ns
fmax
— 3 Clk Frequency, Local Feedback, Same GLB ³
125.0 — 90.0 — 60.0 — MHz
tsuq
— 4 I/O Cell Reg, Data Setup Time, Quadrant I/O Clock
5.0
8.0 — 12.0 — ns
thq
— 5 I/O Cell Reg, Data Hold Time, Quadrant I/O Clock
0.0 — 0.0 — 0.0 — ns
tcoq
A 6 I/O Cell Reg, Quadrant Clock to Output Delay
— 4.0 — 6.0 — 9.0 ns
tsug
— 7 I/O Cell Reg, Data Setup Time, Global Clock
3.5 — 6.0 — 9.0 — ns
thg
— 8 I/O Cell Reg, Data Hold Time, Global Clock
0.0 — 0.0 — 0.0 — ns
tcog
A 9 I/O Cell Reg, Global Clock to Output Delay
— 6.0 — 7.5 — 11.0 ns
tsu1
— 10 GLB Reg Setup, BFM Input to Same BFM GLB, 4 PT Bypass 4.5 — 7.0 — 10.0 — ns
th1
— 11 GLB Reg Hold Time, BFM Input to Same BFM GLB
0.0 — 0.0 — 0.0 — ns
tco1
A 12 GLB Reg, Global Clock to Same BFM Output Delay
— 8.0 — 10.0 — 15.0 ns
tsuceq — 13 I/O Cell Reg, CLKEN Setup Time, Quadrant I/O Clock 5.5 — 6.5 — 9.5 — ns
thceq — 14 I/O Cell Reg, CLKEN Hold Time, Quadrant I/O Clock
0.0 — 0.0 — 0.0 — ns
tsuceg — 15 GLB Reg, CLKEN Setup Time, Global Clock
3.5 — 4.5 — 6.5 — ns
thceg — 16 GLB Reg, CLKEN Hold Time, Global Clock
0.0 — 0.0 — 0.0 — ns
tgoe B/C 17 Global Output Enable/Disable Delay
— 7.0 — 10.0 — 15.0 ns
trglb
— 18 Global Reset/Preset Time, GLB Reg
— 14.0 — 15.0 — 22.0 ns
trio
— 19 Global Reset/Preset Time, I/O Cell Reg
— 8.5 — 10.0 — 15.0 ns
trw
— 20 Global Reset/Preset Pulse Duration
5.0 — 6.5 — 9.5 — ns
twh
— 21 Global or Quadrant Clock Pulse, High Duration
4.0 — 6.0 — 9.0 — ns
twl
— 22 Global or Quadrant Clock Pulse, Low Duration
4.0 — 6.0 — 9.0 — ns
1. Unless noted otherwise, all parameters use PTSA and CLK0.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 20-bit counter with local feedback.
4. Refer to Switching Test Conditions section.
Table 2-0030/81080V
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