81080V Datasheet, PDF (18/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
Example Timing Calculations
tpd1
= (BFM Input Path Delay) + (GLB Delay) + (Output Path Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t4ptcom + tmbp) + (tbfmm + tbcom + tobp + todcom + tslf)
= (#23 + #26 + #61) + (#39 + #42 + #45) + (#64 + #69 + #25 + #35 + #37)
= (0.3 + 0.4 + 1.0) + (2.6 + 0.5 + 0.0) + (0.6 + 1.5 + 0.0 + 1.6 + 0.0)
= 8.5 ns
tpd (within BFM)
= (BFM Delay) + (GLB Delay)
= (tbfmm) + (tandhs + t4ptcom + tmbp)
= (#64) + (#39 + #42 + #45)
= (0.6) + (2.6 + 0.5 + 0.0)
= 3.7 ns
tpd (between BFMs)
= (GRP Delay) + (BFM Delay) + (GLB Delay)
= (tgrpm) + (tbfmg) + (tandhs + t4ptcom + tmbp)
= (#65) + (#67) + (#39 + #42 + #45)
= (2.6) + (3.3) + (2.6 + 0.5 + 0.0)
= 9.0 ns
BFM I/O to internal tri-state Enable/Disable
= (BFM Input Path Delay) + (GLB Delay, 1PT) + (Tri-state Control Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t1pt + tmbp) + (tgrpmz)
= (#23 + #26 + #61) + (#39 + #41 + #45) + (#66)
= (0.3 + 0.4 + 1.0) + (2.6 + 1.9 + 0.0) + (3.6)
= 9.8 ns
tsu1 = (BFM Input Path Delay) + (GLB Setup Time) - (Min. Global Clock Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t4ptreg + tmsu) – (tgck min)
= (#23 + #26 + #61) + (#39 + #43 + #48) – (#78)
= (0.3 + 0.4 + 1.0) + (2.6 + 1.4 + 2.7) – (3.9)
= 4.5 ns
1/Fmax = (Global Clk to MC Output) + (Local Feedback) + (GLB Setup Time)
= (tmco) + (tfloc) + (tandhs + tptsa + tmsu)
= (#47) + (#54) + (#39 + #44 + #48)
= (0.2) + (0.1) + (2.6 + 2.4 + 2.7)
= 8.0 ns
Fmax = 125 MHz
Note: Calculations are based upon timing specifications for the ispLSI 81080V-125L
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