81080V Datasheet, PDF (5/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
Figure 2. ispLSI 8000V GLB Overview
I/O Big Fast Megablock Input Tracks
0
PT 0
PT 1
PT 2
PT 3
AND Array Input
Routing
General Purpose Big Fast Megablock Input Tracks
Feedback Inputs
43
20
Product Term
Sharing Array
PT 4
PT 5
PT 6
PT 7
PT 8
PT 9
PT 10
PT 11
PT 12
PT 13
PT 14
PT 15
Fully Populated
AND Array
Macrocell 0
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
0
PT Reset
Shared PT Clock
Bus Input
To Interconnect
Macrocell 1
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
1
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
To Interconnect
Macrocell 2
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
To Interconnect
2
Macrocell 3
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
To interconnect
3
From Tristate
Bus Track
PT 76
PT 77
PT 78
PT 79
PT 80
PT 81
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
5
Macrocell 19
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
19
PT Reset
Shared PT Clock
Bus Input
To Interconnect
From Tristate Bus Track
To Output Control MUX
Function Selector (E² Cell Controlled)