81080V Datasheet, PDF (20/26 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperBIG™ High Density PLD

Specifications ispLSI 81080V
Signal Descriptions
Signal Name
Description
CLK0, CLK1,
CLK2
Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock
inputs of all GLB registers in the device.
CLKEN
Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for
each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate
the clock to the register.
GND
Ground (GND)
GOE0, GOE1,
GOE2, GOE3
Global Output Enable inputs.
SET/RESET
Dedicated reset/preset pin connected to ALL registers in the device, GLB registers and I/O registers.
Each register can independently choose to be reset or preset when this signal goes active. The active
polarity is user-selectable.
IOCLKEN
Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for
all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the
clock to the I/O register.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
EPEN
Embedded Port Enable Pin – When this pin is high, the port is enabled. When this pin is low, the
state machine is held at reset asynchronously and TCK, TMS and TDI are ignored.
TMS
Input – This signal is the Test Mode Select input signal.
QIOCLK0,
QIOCLK1,
QIOCLK2,
QIOCLK3
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers
on the same side of the device only, they are not connected to all of the I/O registers. Use of these
quadrant I/O clocks gives the fastest tco from the device.
TCK
Input – This signal is the Test Clock input signal.
TDI
Input – This signal is the Test Data input signal.
TDO
Output – This signal is the Test Data Out Output Signal.
TOE
Test Output Enable. Tristates all I/O pins when a logic low is driven.
VCC
Vcc
VCCIO
Power supply for the output drivers. The internal logic of the device is connected to VCC which is
always 3.3V. The output drivers are connected to VCCIO which can be equal to VCC or 2.5V. This
allows the output drivers to be powered from 2.5V, for example, to interface directly with another 2.5V
device.
NC¹
No connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
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