PALLV22V10 Datasheet, PDF (7/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

LOGIC DIAGRAM
CLK/I0 1
(2)
I1 2
(3)
I2 ³
(4)
I3 ⁴
(5)
I4 5
(6)
I5 6
(7)
I6 7
(9)
I7 8
(10)
I8 ⁹
(11)
I9
10
(12)
I ₁₀ 11
(13)
GND 12
(14)
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
0
1
9
D AR _Q
Q
SP
10
11
00
01
0
1
10
10
D AR _Q
11
00
20
Q
01
SP
21
33
0
1
R_{D AR Q}
O_Q
F ^SP
10
11
00
01
34
48
49
65
66
82
83
97
98
USE ^{GANLEDWEDVEICSEIGSNS}
0
1
D AR _Q
Q
SP
10
11
00
01
0
1
D AR _Q
Q
SP
10
11
00
01
0
1
D AR _Q
Q
SP
10
11
00
01
0
1
D AR _Q
Q
SP
10
11
00
01
0
1
10
D AR _Q
11
00
Q
01
110
SP
0
1
111
10
D AR _Q
11
00
121
Q
SP
01
122
130
131
0
1
D AR _Q
Q
SP
10
11
00
01
0
1
SP
0
34
78
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
24
(28) ^VCC
23 I/O9
(27)
22 I/O8
(26)
21 I/O ₇
(25)
20 I/O 6
(24)
19 I/O5
(23)
18 I/O 4
(21)
17 I/O3
(20)
16 I/O2
(19)
15 I/O 1
(18)
14 I/O 0
(17)
13 I11
(16)
18956D-006
PALLV22V10 and PALLV22V10Z Families
7