PALLV22V10 Datasheet, PDF (3/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

Variable Input/Output Pin Ratio
The PALLV22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to V_CC or GND.
Registered Output Configuration
Each macrocell of the PALLV22V10 includes a D-type flip-flop for data storage and synchronization.
The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered
configuration (S₁ = 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses
FOR ^{the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.}
CLK
ES _AR
IC _NS D Q
EV ^{IG Q}
SP
L ^{D ES 0}
USE ^{GANEW D 1}
10
11
00
01
S₁
S₀
I/O_n
S₁
S₀
Output Configuration
0
0
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
1
Combinatorial/Active High
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
18956C-004
PALLV22V10 and PALLV22V10Z Families
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