PALLV22V10 Datasheet, PDF (4/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

AR
DQ
CLK
Q
SP
S₀ = 0
S₁ = 0
S₀ = 0
S₁ = 1
a. Registered/active low
b. Combinatorial/active low
S₀ = 1
R _AR
S₁ = 0
S₀ = 1
S₁ = 1
FO _{D Q}
S CLK
Q
E _SP
IC _{NS c. Registered/active high}
d. Combinatorial/active high
EV ^IG _{Figure 2. Macrocell Configuration Options}
18956D-005
D _{ES Programmable Three-State Outputs}
L _{D Each output has a three-state output buffer with three-state control. A product term controls the}
A _{buffer, allowing enable and disable to be a function of any product of device inputs or output}
G ^W feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as
E ^{a dedicated input if the buffer is always disabled.}
SE ^{N Programmable Output Polarity}
U ^{The polarity of each macrocell output can be active high or active low, either to match output}
signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is controlled by programmable bit S₀ in the output macrocell, and affects both registered
and combinatorial outputs. Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same polarity, the output is
programmed to be active high (S₀ = 1).
Preset/Reset
For initialization, the PALLV22V10 has additional preset and reset product terms. These terms are
connected to all registered outputs. When the synchronous preset (SP) product term is asserted
high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition.
When the asynchronous reset (AR) product term is asserted high, the output registers will be
immediately loaded with a LOW independent of the clock.
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PALLV22V10 and PALLV22V10Z Families