PALLV22V10 Datasheet, PDF (16/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been
powered up. The output state will depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V_CC can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
x The V_CC rise must be monotonic.
x Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
t_PR
Power-Up Reset Time
Parameter Description
R_Max
FO ¹⁰⁰⁰
Unit
ns
t_S
t_WL
Input or Feedback Setup Time
S ^{Clock Width LOW}
EVICEIGNS ^Power
D ^{S Registered}
E ^Active-Low
Output
USE ^{GANLEW D Clock}
2.7 V
t_PR
t_S
t_WL
See Switching
Characteristics
V_CC
18956D-018
Figure 3. Power-Up Reset Waveform
16
PALLV22V10 and PALLV22V10Z Families