PALLV22V10 Datasheet, PDF (6/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

Quality and Testability
The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS
PALLV22V10 allows direct testing of the device array to guarantee 100% programming and
functional yields.
Technology
The high-speed PALLV22V10 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are designed
to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes,
output slew-rate control, and a grounded substrate for clean switching.
Zero-Standby Power Mode
R _{The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an}
O extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down
F ^{most of its internal circuitry. The current will go to almost zero (I}_CC ^{<30 µA). The outputs will}
maintain the states held before the device went into the standby mode.
S _{If a macrocell is used in registered mode, switching pin CLK/I0 will not affect standby mode status}
E _{S for that macrocell. If a macrocell is used in combinatorial mode, switching pin CLK/I0 will affect}
IC ^{standby mode status for that macrocell.}
V ^{N This feature reduces dynamic I}CC ^{proportionally to the number of registered macrocells used. If all}
E ^{IG macrocells are used as registers and only CLK/I0 is switching, the device will not be in standby}
D ^{S mode, but dynamic ICC will typically be <2 mA. This is because only the CLK/I0 buffer will draw}
current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz)
E _{under these same conditions.}
AL ^{D When any input switches, the internal circuitry is fully enabled, and power consumption returns}
to normal. This feature results in considerable power savings for operation at low to medium
G ^W _frequencies.
E ^E _{Product-Term Disable}
S ^N _{On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut}
U _{off from these product terms so that they do not draw current. Product-term disabling results in}
considerable power savings. This saving is greater at the higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
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PALLV22V10 and PALLV22V10Z Families