PALLV22V10 Datasheet, PDF (5/19 Pages) Lattice Semiconductor – Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

Note that preset and reset control the flip-flop, not the output pin. The output level is determined
by the output polarity selected.
Benefits of Lower Operating Voltage
The PALLV22V10 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3 V designs facilitate a reduction in the form factor.
R ^{A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise}
generation and provides a less hostile environment for board design. A lower operating voltage
FO ^{also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.}
3.3-V (CMOS) and 5-V (CMOS and TTL) Compatible Inputs and I/O
S _{Input voltages can be at TTL levels. Additionally, the PALLV22V10 can be driven with true 5-V}
E _{S CMOS levels due to special input and I/O buffer circuitry.}
IC _{N Power-Up Reset}
EV ^{IG All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the}
PALLV22V10 will depend on the programmed output polarity. The V_CC rise must be monotonic,
D ^{S and the reset delay time is 1000ns maximum.}
L ^{E Register Preload}
A ^D The registers on the PALLV22V10 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
G ^W _{making it unnecessary to cycle through long test vector sequences to reach a desired state. In}
E ^{E addition, transitions from illegal states can be verified by loading illegal states and observing}
S ^{N proper recovery.}
U ^{Security Bit}
After programming and verification, a PALLV22V10 design can be secured by programming the
security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern
by a device programmer, securing proprietary designs from competitors. When the security bit is
programmed, the array will read as if every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of the entire pattern.
Programming and Erasing
The PALLV22V10 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
PALLV22V10 and PALLV22V10Z Families
5