ISL6534 Datasheet, PDF (9/26 Pages) Intersil Corporation – Dual PWM with Linear

Pin Description
24-PIN TSSOP
TOP VIEW
FB1 1
COMP1 2
COMP2 3
FB2 4
REFIN 5
REFOUT 6
SS1/EN1 7
SS2/EN2 8
SS3/EN3 9
VREF 10
DRIVE3 11
FB3 12
GND
BOTTOM
SIDE PAD
24 VCC
23 BOOT1
22 UGATE1
21 VCC12
20 LGATE1
19 LGATE2
18 PGND
17 UGATE2
16 BOOT2
15 GND
14 PGOOD
13 FS_SYNC
ISL6534
32 LD 5x5 QFN
TOP VIEW
32 31 30 29 28 27 26 25
REFIN 1
24 UGATE1
NC 2
23 PGND_1
REFOUT ³
SS1/EN1 ⁴
SS2/EN2 ⁵
SS3/EN3 6
GND
BOTTOM
SIDE PAD
22 VCC12_1
21 LGATE1
20 LGATE2
19 VCC12_2
VREF 7
18 PGND_2
DRIVE3 8
17 NC
9 10 11 12 13 14 15 16
VCC
This power pin supplies bias to the control functions. It can
be connected to a nominal 5V (±10%) supply, or it can
function as a shunt regulator (nominal 5.8V), with an external
pull-up resistor (nominally 150Ω to 12V).
GND
This pin is the signal ground for the IC. The metal thermal
pad under both packages is connected to the GND potential
(through the IC substrate; the pad does NOT substitute for
the GND pin connection). But the GND pin and the metal
pad should be connected together on the board, and tied to
a good GND plane (both for electrical and thermal
conduction). Note that the thermal pad on both packages
limits metal interconnect traces underneath the package.
VCC12 (QFN: VCC12_1, VCC12_2)
This power pin (nominal 12V) supplies the output gate
drivers, as well as some other control functions.
The QFN package has two power pins; one for each
switcher. They are electrically connected internally, but allow
for separate decoupling caps to better isolate the switching
noise, if necessary. Even if they share one capacitor, they
should both be connected externally, for lower resistance.
NOTES:
6. BOOT2 and UGATE2 are different order in QFN.
7. NC is No Connect
PGND (QFN: PGND_1, PGND_2)
This pin is the Power GND for the gate drive circuits. It is not
directly tied to GND inside the IC; it should be tied to GND
on the board.
The QFN package has two Power GNDs; one local to each
switcher; both should be connected externally to the GND
plane on the board.
SS1/EN1, SS2/EN2, SS3/EN3
These analog input pins have two functions. A 30µA current
source charges an external capacitor (to GND), to provide a
soft-start timing ramp; their respective Output voltage will
follow the ramp voltage as it powers up. The 2nd function is
Enable; when the input is left open (with the soft-start cap),
the respective output will be Enabled after the ramp reaches
the 1V level. If the input is pulled to a low logic level, the
output will be disabled.
SS2/EN2 also has a special mode function; see Table 1.
Tying it to VCC (5V) selects the DDR mode (where both
OUT1 and OUT2 share the SS1 ramp); otherwise it will be in
the Independent mode.
COMP1, COMP2
These analog output pins are used to externally compensate
the error amplifiers for their respective regulators.
9
FN9134.1