ISL6534 Datasheet, PDF (10/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
FB1, FB2, FB3
These analog input pins are used to set their respective
regulator output voltages. A resistor divider from the output
to GND is compared to a reference voltage (0.6V for OUT1
and OUT3; REFIN pin for OUT2). The compensation
components also connect to these pins.
UGATE1, UGATE2
These output pins provide the gate drive for the upper
MOSFETs of OUT1 and OUT2 respectively; the voltage
comes from its bootstrap pin, typically 12V (minus the diode
drop) above the VCC12 pin.
LGATE1, LGATE2
These output pins provide the gate drive for the lower
MOSFETs of OUT1 and OUT2 respectively; the voltage
comes from VCC12.
BOOT1, BOOT2
These pins feed the bootstrap voltage (externally generated
with a diode and a capacitor) to the upper MOSFETs,
through the UGATE pins. Either BOOT pin can be connected
directly to a power supply instead (but only if the VIN voltage
of the regulator is sufficiently lower than that supply, such
that the FETs have enough gate-source voltage).
REFIN
This analog input is used as the reference voltage for OUT2
(the error amplifier compares it to the feedback resistor
divider). This voltage is also fed into a buffer, which is output
on the REFOUT pin.
REFOUT (VTT Buffer)
This analog output provides a buffered version of the REFIN
input, to be used by other IC’s in the system. In the DDR
mode, where VTT is generated from VDDQ, this output can
be used as a VTT Buffer.
In addition, it can be used to select the phase relationship,
but it disables the buffer in that case (see Table 1). Tying it to
VCC (5V) selects 0 degrees phase (in either mode); leaving
it open (where it can also be used as a reference output)
selects 90 degrees phase (in DDR mode) and 180 degrees
phase (in Independent Mode). A capacitor to GND is
recommended for stability (see Application Considerations).
VREF
This analog output pin is a 3.3V reference, which can be
used by this IC (or others) as a voltage reference. A
capacitor to GND is recommended for stability (see
Application Considerations).
DRIVE3
This pin drives the gate of an external N-Channel MOSFET,
for OUT3, which is a linear regulator.
PGOOD
This digital output is an open-drain pull-down device. When
power is first applied to the IC, the output is pulled low, for
power “Not Good”. After all 3 Soft-Start pins complete their
ramp up with no faults (no short detected on switchers) the
power is considered “Good”, and the output pin is high-
impedance (to be pulled up to a logic high level with an
external pull-up resistor). See the PGOOD section under
Functional Description for more details.
FS/SYNC
This input allows the user to adjust the internal oscillator
used for the PWM outputs; a pull-down resistor will speed up
the oscillator. In addition, a digital clock signal can be fed into
this input, in order to SYNC its clock with the external one;
this allows the clock edges to line up in a way that won’t
interfere with each.
PINOUT NOTE:
Note that the pin order of UGATE2 and BOOT2 are different in the
two packages, due to bonding optimization. The QFN package also
adds an extra VCC12 and PGND pin, and has additional No
Connection pins.
Functional Description
Overview
There are two single-phase synchronous buck converters,
and one linear regulator. Except for a common clock, the two
PWM regulators are independent. Refer to Figures 2 and 3
for a quick discussion of the circuit. The right side of the
diagram shows the 3 output stages with their components;
each switcher has an upper and lower FET, input capacitor,
bootstrap diode and capacitor, an LC output filter, and an
optional snubber.
The 3rd regulator (OUT3) is a linear, with an external NFET,
input and output capacitor. The output voltage is divided to
FB3, and compared to an internal 0.6V reference. An RC is
used for compensation.
The left side of the diagrams show the various control and
programming components. Each switcher has a compensation
network for stability that includes the output resistor divider.
VREF and REFOUT can be used as reference voltages. There
are three SS/EN pins to set the soft-start ramp of each output,
and a PGOOD output to signal when they are all done. The
FS_SYNC pin allows options for the oscillator frequency. Each
of these features will be described in more detail, either in the
Functional Description or the Application Considerations.
The first regulator (OUT1) has an internal 0.6V reference. To
set the output voltage level, connect a resistor divider
between VOUT1 and FB1.
The second regulator (OUT2) requires an external reference
connected to REFIN. For DDR memory applications
(Figure 2), connect a divide-by-two resistor divider from
VOUT1 to ground with the center point connected to REFIN.
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FN9134.1