ISL6534 Datasheet, PDF(17/26 Page) Intersil Corporation

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ISL6534 Datasheet, PDF (17/26 Pages) Intersil Corporation – Dual PWM with Linear

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ISL6534

Connecting One Input from Another Output

Often, one of the 3 outputs generated is used as the input

voltage to a 2nd (and perhaps 3rd); the general case

includes input or outputs of other IC regulators as well. This

can be done, with a few precautions in mind.

1. The first output must be designed and sized for its own

load current, plus the expected input current of the other

channels.

2. The sequencing of the outputs must be consistent. The

first output cannot be disabled or have a much slower

SS/EN ramp than the input channel, in order to take full

advantage of the soft-start. If the VIN is not present when

the 2nd regulator tries to start up, that can be interpreted

as a short-circuit, and the whole IC could be shut down.

3. The output capacitor of the first is now also the input

capacitor of the 2nd, so it needs to be chosen and sized

for both conditions. For example, transients on the first

output show up on the input of the 2nd; and input current

transients on the 2nd can affect the output of the first.

There may also be trade-offs of the placement of the

various capacitors; some might be near the output FETs

of the first, and some near the input FETs of the 2nd.

4. The linear regulator has no short-circuit protection.

However, if VIN3 is connected to one of the switcher

outputs, a short on the linear output may be detected; but

it is subject to all the cautions mentioned in the SHORT-

CIRCUIT PROTECTION section.

Feedback Compensation

The compensation required for VOUT1 and VOUT2 is similar

to many other switching regulators, and the same tools can

be used to determine their component values. Note that

VOUT1 and VOUT2 are similar with respect to the

compensation; the only difference is their reference voltages

(fixed 0.6V versus REFIN, which does not directly affect the

component values). The schematics show type 3

compensation, but the simpler type 2 is also possible, under

the right conditions. It is recommended to have footprints for

the Type 3, in case it is ever needed; the type 2 is a subset of

that. A simple rule of thumb is that when bulk capacitors are

used on the outputs, the ESR is often high enough (10âs -

100mâ¦) to use Type 2 compensation. But if only ceramic

capacitors (ESR ~ 1âs mâ¦) are used on the outputs, then

most likely Type 3 will be required. Note that the component

labels match the equations given in this section, but may not

match other diagrams in this datasheet.

Figure 15 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (VE/A) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output filter

(LO and CO).

The modulator transfer function is the small-signal transfer

function of Vout/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage âVOSC.

OSC

VIN

DRIVER

PWM

COMPARATOR

âVOSC

DRIVER

ZFB

VE/A

ZIN

ERROR REFERENCE

AMP

PHASE

ESR

(PARASITIC)

VOUT

DETAILED COMPENSATION COMPONENTS

ZFB

VOUT

ZIN

C3 R3

COMP

ISL6534

REF

FIGURE 15. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

MODULATOR BREAK FREQUENCY EQUATIONS

FLC=

------------------1--------------------

2Ï â¢ LO â¢ CO

FESR=

----------------------1----------------------

2Ï â¢ (ESR â¢ CO)

The compensation network consists of the error amplifier

(internal to the ISL6534) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing

frequency (f0dB) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f0dB and

180o. The equations below relate the compensation

networkâs poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 15. Note again that the

component names from Figure 15 apply to the equations

below; they may be labeled with different names elsewhere

in this document. Use these guidelines for locating the poles

and zeros of the compensation network:

FN9134.1

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