ISL6534 Datasheet, PDF (18/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
----------------¹------------------
2π • R2 • C1
F_Z2
=
--------------------------¹---------------------------
2π • (R1 + R3) • C3
F_P1
=
--------------------------¹----------------------------
2
π
•
R2
•


C^-C----1^-1----+^{•-----CC-----22--}
F_P2
=
----------------¹------------------
2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole
(~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 16 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 16. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 16 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2/R1)
0
20LOG
(V_IN/∆V_OSC)
-20
MODULATOR
GAIN
-40
F_LC
F_ESR
-60
10
100
1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 16. ASYMPTOTIC BODE PLOT OF CONVERTER
GAIN
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with -
20dB/decade slope and a phase margin greater than 45^o.
Include worst case component variations when determining
phase margin.
FET Selection (VOUT1, VOUT2)
The typical FET expected to be used will have a low r_DS(ON)
(5-10mΩ) and a low Vgs (Gate-to-source threshold voltage;
1-2V). It can be packaged in a thermally enhanced SO-8 IC
package (where the drain leads are thermally connected to
the leadframe under the die, or similar approaches), or even
in more conventional power packages (D-PAK). If the FETs
are surface mounted to the PCB, with only the area of the
power planes to conduct the heat away, then the maximum
load current will be limited by the thermal ratings under those
conditions. Using conventional heatsinks or sufficient airflow
can extend the limit of dissipation.
FETs can be paralleled for higher currents; this spreads the
heat between the FETs, which helps keep the temperature
lower. However, the gate driver is now driving twice the gate
capacitance, so there will be more dissipation in the ISL6534
gate drivers.
Typical values for maximum current (based on 8-pin SOIC
FETs surface-mounted on PCB, with no heatsinks or airflow)
are 5A for a dual FET; 10A for single FETs for upper and
lower; and 20A for two FETs in parallel for both upper and
lower. These are just rough numbers; many factors affect it,
such as PCB board area available for heatsinking planes,
how close other dissipative devices are, etc.
In general (and especially for short UGATE duty cycles, such
as converting 12V input down to 1V or 2V outputs), the
upper FET should be chosen to minimize the Gate charge,
since switching losses dominate. Since the lower FET is on
most of the time, low r_DS(ON) should be the main
consideration.
The ISL6534 requires 2 N-Channel power MOSFETs for
each switcher output. These should be selected based upon
r_DS(ON), gate supply requirements, and thermal
management requirements. The following are some
additional guidelines.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only the
upper MOSFET has switching losses, since the FET body
diode (or optional external Schottky rectifier) clamps the
switching node before the synchronous rectifier turns on.
P_UPPER
=
I_O2
x
r_DS(ON)
x
D
+
1
2
Io x V_IN x t_SW x Fs
P_LOWER = I_O2 x r_DS(ON) x (1 - D)
Where: D is the duty cycle = V_O/V_IN,
t_SW is the switching interval, and
Fs is the switching frequency.
18
FN9134.1