ISL6534 Datasheet, PDF (3/26 Pages) Intersil Corporation – Dual PWM with Linear

Block Diagram
SS1/EN1
SS2/EN2
SS3/EN3
VCC5
30 µA
VCC5
30 µA
VCC5
30 µA
3.3V
ISL6534
VCC
POWER
ON
RESET
AND CONTROL
VREF
VCC5
5.8V
REFERENCE 3.3V
BIAS CURRENT
0.6V
3.3V
PGOOD =
all 3 SS ramps done
with no COMP short
CLOCK AND
SAWTOOTH
GENERATOR
PGOOD
COMP1
FB1
REFIN
FB2
COMP2
0.6V
3.3V
1-2 CLOCK
CYCLE
FILTER
MONITOR
IF SHORT > FILTER,
COMP PINS SHUT DOWN ALL
FOR SHORTS 3 OUTPUTS
VCC12
BOOT1
OUTPUT1
DRIVERS
GATE CONTROL
LOGIC
DEAD-TIME
CONTROL
UGATE1
LGATE1
BOOT2
OUTPUT2
DRIVERS
GATE CONTROL
LOGIC
DEAD-TIME
CONTROL
UGATE2
LGATE2
FS/SYNC
REFOUT
0.6V
FB3
DRIVE3
GND
PGND
FIGURE 1. BLOCK DIAGRAM
3
FN9134.1