ISL6534 Datasheet, PDF (13/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
Cases 3 and 4 don’t apply for DDR.
Case 1 (divide both signals):
REFIN = VOUT1*R4/(R3+R4)
FB2 = VOUT2*R2/(R1+R2)
Case 2 (divide VOUT1):
REFIN = VOUT1*R4/(R3+R4)
FB2 = VOUT2 (no R2)
Soft-Start/Enable
Numerous combinations of independent and dependent
startup are possible by the various methods of connecting
the three EN/SS pins; some combinations are shown in
Figures 7 and 8. In Figure 7, the three regulators enable
independently and rise at rates selected by their individual
soft-start capacitors C_SS1, C_SS2, and C_SS3. In Figure 8, two
diodes are used to connect to a single open-drain pull-down
device (not shown); this allows one FET to disable both
channels. When enabled, they will each rise at their own
ramp rate. If they could use the same ramp rate, then both
pins could share one capacitor and the one FET, and the
diodes are not necessary. The 3rd channel is disabled and
ramped independently. Note that since the EN trip point is
around 1V, some care should be taken to guarantee the
diode drop and the FET in series with it will always be
below it.
OPEN-DRAIN
LOGIC SIGNALS
EN1
SS1/EN1
SS2/EN2
EN2
SS3/EN3
EN3
C_SS1
C_SS2
C_SS3
FIGURE 7. CONNECTIONS FOR INDEPENDENT ENABLE
AND SOFT-START
OPEN-DRAIN
LOGIC SIGNALS
EN1, 2
SS1/EN1
SS2/EN2
SS3/EN3
EN3
C_SS1
C_SS2
C_SS3
FIGURE 8. 1 AND 2 ENABLED TOGETHER BUT HAVE
INDEPENDENT SOFT-STARTS. 3 IS FULLY
INDEPENDENT.
The soft-start pins can share the same capacitor, to ramp
them all at the same rate (but since there will be 3 times the
current, the value of the capacitor needs to be approximately
3 times bigger, for the same ramp rate).
Note that each output rise does not start until its SS/EN
voltage reaches ~1V; the output will then start to ramp up
until the soft-start is > ~3.3V (ramp is done). PGOOD will not
go active unless all three ramps are >3.3V (and no faults are
detected).
Figure 9 shows the start-up waveform for VOUT1 at power
up. In this example, the VCC voltage is generated from the
internal shunt regulator. The ramp of the 12V is controlled by
the external power supply; it can vary widely, depending
upon the type and model used. The ramp of the shunt more
or less follows the VCC12 until it reaches its regulation point
at ~5.8V. Both VCC and VCC12 must be past their rising
POR trip points before SS1 starts rising. The order doesn’t
matter, and may be different, especially when the VCC uses
an independent supply.
VCC12 ~8V
4: VCC12
2: SS1/EN1
3: VCC
SS1 ~1V
1: VOUT1
FIGURE 9. STARTUP (VCC12, VCC, SS1/EN1, VOUT1)
When SS1 reaches ~1V, the output starts up (the switching
noise becomes apparent then). Note that if VIN1 is tied to a
supply other than either VCC or VCC12, then it MUST be up
above the desired output voltage (or at least ramping there
ahead of the output) before the SS/EN1 reaches ~1V. If not,
the short-circuit protection will trigger, and shut down all
three outputs, requiring a POR on either VCC or VCC12 to
restart. If either VCC or VCC12 is used as VIN, then the
voltage levels should be sufficient, as long as the design can
function at the POR levels, since both must hit their POR
levels before starting up. So, for example, if the VCC12
supply was also used as VIN, then as long as the output
could start up at VIN = ~8V (the VCC12 rising POR trip
point) the start-up condition is satisfied.
PGOOD
The open-drain pull-down device is on when power is first
applied to the IC, forcing the pin to a logic low, for power “Not
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FN9134.1