ISL6534 Datasheet, PDF (16/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
SS_EN Capacitors
The basic formula for the soft-start is:
t
=
C•
d_----V_---
I
where
t is the soft-start ramp time
C is the external capacitor to GND on the SS pin
dV is the voltage the ramp charges up to
(nominal value is 3.3V)
I is the charging current (nominal 30µA).
Or:
time (in ms) = 110 * C (in µF).
Plugging in the known values, and adjusting units, time (in
ms) = 110 * C (in µF). So, for example, a 0.1µF capacitor will
give a ramp time of 11ms, and a 1.0µF capacitor will give a
ramp time of 110ms, which is around the practical maximum
value allowed, before noise and leakage and other factors
start changing the formula. Faster ramps are allowed, as
long as the input supplies are capable of charging the output
capacitors (and possibly the load currents, if present at
power-up), without drooping too much (for example, if either
the 5V or 12V supply is dragged down below its POR falling
trip point, because of output loading, that might imply that
the output ramp is too fast (or perhaps bigger input
capacitors are needed, or possibly other explanations as
well).
Note that the above formula determines how long the Soft-
Start ramp time is. But since the outputs don’t turn on until
the SS/EN pin reaches ~1V, that means the actual time the
output ramps is only ~70% of the total SS ramp.
Note that each of the three regulators can have its own
independent ramp rate, as well as their own independent
enable function (pulling one of the SS_EN pins below 1V
nominal will shut down that output). Two or three pins can be
tied together to share a common ramp and enable; but note
that there are now two or three times the current charging a
single cap, so the formula should be adjusted accordingly. If
you need the same ramp rate, but separate enable functions,
then don’t share the capacitor; just use the same value
capacitor on each, which will still allow independent
enabling. If you need different ramp rates, but want to share
a single enable signal, you will probably need to connect a
separate pull-down FET to each pin, and just drive their
gates from a common signal, or use diodes to isolate a
single FET to multiple pins (as previously shown in Figures 7
and 8).
VREF/REFOUT Capacitors
The VREF output may require a small capacitor to GND to
remain stable; 1.0µF is recommended. If the output is not
used (for example, in DDR mode, where if VOUT1 is divided
down for REFIN); it could be left open, but the additional
noise and current draw may be objectionable. So even then,
a capacitor is recommended.
The REFOUT output is similar; a 0.1µF capacitor is
recommended. If the output is not used, it could be left open,
but the additional noise and current draw may be
objectionable. So even then, a capacitor is recommended.
Linear (VOUT3) Component Selection
Once the VIN3 and VOUT3 levels are defined, the NFET is
chosen to handle the output load current and the power
dissipation it creates. The power is determined by:
Power = (VIN3 – VOUT3) • ILOAD
Even if the FET is in a good thermal package (such as a
D-PAK), the mounting of the FET will determine how much
power dissipation is allowed. If simply placed on a pad on an
FR4 board, the dissipation will be limited by the area of the
pad; the more area, the lower the temperature will be. The
recommendation is to use large plane areas, as well as
thermal vias to the back of the board, plus additional area
there, if possible. Even then, power dissipation is usually
limited to 1W or so, which would give 1A (assuming a 1V
drop from VIN3 to VOUT3). See Figure 14.
VIN3
DRIVE3
FB3
R3 _C3
R1
R2
CIN3
VOUT3
COUT3
FIGURE 14. LINEAR (VOUT3) REGULATOR COMPONENT
SELECTION
The output capacitor C_OUT3 should be chosen for output
filtering and transient response needs. However, the output
capacitor also affects the stability of the regulator, so the
choice is limited to a range of acceptable values, which
include the capacitance and its ESR (Effective Series
Resistance).
The input capacitance C_IN3 is chosen to keep the input
supply from changing too much when the output current load
changes; this is related to transient response.
The resistor ratio is chosen to divide the desired output
voltage down to make the FB3 pin = 0.6V. A typical value of
1kΩ for the combined resistance is a good starting value.
The full equation is VOUT3*(R2/(R1+R2) = FB3 = 0.6V.
Compensation components R3 and C3 are chosen to make
the output stable under the conditions being used. Choose
the values to add a zero around 30kHz to cancel a pole.
Values of 4.75K and 6800pF are a good starting point.
NOTE: If the Linear output is not used, leave SS/EN3 open (or tie to
SS1 or SS2); and tie DRIVE3 to FB3, with no other components; this
should disable VOUT3, but keep PGOOD active for VOUT1 and
VOUT2.
16
FN9134.1