ISL6534 Datasheet, PDF (15/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
Short-Circuit Protection
There is no current sensing or r_DS(ON) sensing or Under-
Voltage sensing on the ISL6534. However, if either Channel
1 or 2 output is shorted while active, there is a simple
detection on the error amp COMP output that implies either
Over-Current or Under-Voltage; the PGOOD pin goes low
immediately. If the condition persists for 1-2 internal clock
cycles (3-6µs at 300kHz), then ALL 3 Outputs are latched
off, requiring either a VCC or VCC12 POR to restart. The
protection was not designed to work for the case of powering
up an output into a short-circuit, and there are limitations on
detecting applied shorts. Note that the linear regulator has
no short-circuit protection.
See Application Considerations for more details.
Oscillator
The internal oscillator is nominally 300kHz (±20% tolerance)
with no external components required, as measured at either
of the LG or UG pins. To run faster, a resistor from FS_SYNC
pin to GND will speed up the frequency. See Figure 12 for a
curve that shows the frequency versus resistor value. Note
that the curve is steep as it approaches 300kHz; operation in
this area is not recommended. Since this pin has several
functions muxed onto it, it is important that they do not
interfere with each other. Thus, the circuit that looks for the
resistor will shut off (and default to the 300kHz) if it doesn’t
see a current in the expected range. There should not be any
excessive capacitive loading on the pin either, and if a
resistor is used, it should be located very close to the
FS_SYNC pin.
400
350
300
250
200
150
100
50
0
1
1.5
2
2.5
3
3.5
PERIOD (µs)
FIGURE 12. TYPICAL CLOCK PERIOD vs FS_SYNC
RESISTOR TO GND
SYNC
With multiple switching regulators running on the same
board at similar, but independent frequencies, there may be
interference between them; a “beat” frequency can develop,
based on the difference between the two frequencies. To
avoid this situation, the ISL6534 has a synchronization
circuit that will read an external frequency, and make the
ISL6534 follow it. The typical circuit involves taking the LG
(Lower Gate) signal from another regulator, going through a
series 10kΩ resistor (to limit the current), and connecting to
the FS_SYNC pin (with no other resistors attached). Within a
few internal clock cycles, the ISL6534 will lock-in to the new
frequency, and run normally as if it were programmed to run
there. If the signal is lost for any reason, after a set number
of clock cycles, the ISL6534 will go back to its default internal
frequency. Note: Do not use the oscillator of another
regulator directly, since the ISL6534 will scale it up by 4 to
match its own internal oscillator; using the LGATE signal will
allow the ISL6534 to match its LGATE to the same
frequency. See Figure 13.
Note that the SYNC circuit expects to see a stable frequency,
and can be fooled by variations. For example, if the gate
signal used has both leading and falling edge modulation, or
an extreme duty cycle, that might cause some confusion.
Skipping clock cycles completely may also be misinterpreted
as a much longer period. The SYNC circuit was designed to
work over a range of 350kHz to 850kHz.
ISL6534
OTHER
REGULATOR
VIN1
UGATE1
VOUT1
FS_SYNC
LGATE1
RFS
FIGURE 13. CONNECTION OF FS_SYNC TO THE LGATE OF
ANOTHER SWITCHING REGULATOR
Application Considerations
Decoupling Capacitors
Both the VCC12 and VCC pins should have a decoupling
ceramic capacitor (typical values are 1 - 10µF), located as
near to the pin as possible, and with the GND connection as
a via to a wide GND plane. A low-value resistor in series with
the capacitor may help isolate the switching noise from the
power supply from affecting the capacitor, especially if either
pin is sharing a power supply with other noisy circuits (but
adding a resistor in series with the shunt regulator resistor
gives no advantage).
15
FN9134.1