ISL6534 Datasheet, PDF (23/26 Pages) Intersil Corporation – Dual PWM with Linear

ISL6534
will get a clean shutdown; see also #6. In addition, the
higher VOUT for a given VIN will give a higher UGATE
duty cycle, and the average COMP voltage is higher, so it
doesn’t have as far to go to trip.
6. In general, the faster the rise time of the output current
during the short, the more current will be allowed on the
initial peak, and the better chance the COMP pin will have
a sharp rise as well. A low resistance short (#4) and a
higher output voltage (#5) both help. However, if the
current ramps too fast, then a false trip is also possible
(shutting down at a current level still within the expected
load range).
7. The load current at the time of the short can affect the
results; the response of a short can be different at no load
versus full load.
8. The compensation components are chosen to stabilize
the regulation loop; however, if they unnecessarily load
the COMP output, that could affect the trip point
response.
9. The output capacitance and its ESR can affect how
quickly the current ramps up during a short.
10. Other variables that may contribute to a lesser degree
include variations in the COMP comparator and filter, the
inductor L and DCR, the r_DS(ON) of the FET, the FB
resistor dividers, the error amp reference voltage, the
oscillator frequency, switching noise, VCC voltage,
ambient temperature and airflow, and the layout of the
PCB.
11. Adding external circuitry to sense a fault may be possible,
but subject to the usual limitations of those circuits. For
example, sensing the output or FB voltage doesn’t always
directly correlate with output current.
So the recommendations are as follows:
1. If there is a specific fault condition that needs protection,
try it out first under controlled conditions, either on an
EVAL board, the final circuit, or something close to it,
along with the power supply that will also be used.
Monitor VCC12 and VCC (to be sure they aren’t tripping
POR), the output and the COMP pin. A current probe
monitoring the output current is also very useful.
2. Compare the short circuit resistance to the nominal load
resistance; if they are too close, the circuit may not work
well. Calculate how long the FETs can sit at the higher
current. Is the short more likely from zero load or full
load?
3. Check the rise time of the short circuit current, and what
happens if when the short is released.
4. From the waveform of the COMP pin, see if the values
can be optimized for the short condition. Within the
constraints of the stability criteria, smaller caps (in
general) may give a quicker response.
5. Note that the linear output has no protection at all.
PCB Layout Considerations
General Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
V_IN
ISL6534
UGATE
Q1
L_O
V_OUT
Q2
LGATE
PGND
C_IN
C_O
RETURN
FIGURE 21. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 21 shows the critical power components of the
converter, for either output channel. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in Figure 21 should be
located as close together as possible. Please note that the
capacitors C_IN and C_O each represent numerous physical
capacitors. Locate the ISL6534 within 1-2 inches (or even
less, if possible) of the MOSFETs, Q1 and Q2. The circuit
traces for the MOSFETs’ gate and source connections from
the ISL6534 must be sized to handle up to 1.5A peak
current.
Figure 22 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on each of the SS pins and locate the
capacitors, C_ss close to the SS pin because the internal
current source is only 30µA. Provide local V_CC12 decoupling
between VCC12 and PGND pins, as well as the VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT pin and PHASE node. Note that the PGND pins
are used only for the gate drivers and other output circuitry
(including the VCC12 decoupling capacitor); the GND pins
are used by the VCC pin, and the control circuitry. They
should be joined at a common point.
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FN9134.1