ISL6377 Datasheet, PDF (8/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
Pin Descriptions (Continued)
PIN NUMBER
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
PHASEX
LGATEX
PWM2_NB
FCCM_NB
PGOOD_NB
COMP_NB
FB_NB
VSEN_NB
ISUMN_NB
ISUMP_NB
ISEN1_NB
GND (Bottom Pad)
DESCRIPTION
Phase connection of the programmable internal driver used for either Channel 3 of the Core VR or
Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Current return path for the high-side MOSFET gate driver of the floating internal driver. Connect the
PHASEX pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the
output inductor of either Phase 3 of the Core VR or Phase 1 of the Northbridge VR based on the
configuration state selected.
Low-side MOSFET gate driver portion of floating internal driver used for either Channel 3 of the Core VR
or Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Connect the LGATEX pin to the gate of the low-side MOSFET(s) for either Phase 3 of the Core VR or Phase
1 of the Northbridge VR based on the configuration state selected.
PWM output for Channel 2 of the Northbridge VR. Disabled when ISEN2_NB is tied to +5V.
Diode emulation control signal for Intersil MOSFET Drivers. When FCCM_NB is LOW, diode emulation at
the driver this pin connects to is allowed. A resistor from FCCM_NB pin to GND configures the PWM_Y
and floating internal gate driver [BOOTX, UGATEX, PHASEX, LGATEX pins] to support Phase 3 of the Core
VR and Phase 1 of the Northbridge VR. The FCCM_NB resistor value also is used to set the slew rate for
the Core VR and Northbridge VR.
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VDDP or 3.3V through a resistor.
Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset
voltage and is used to set the switching frequency for the Core VR and Northbridge VR.
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor
die.
Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
Non-inverting input of the transconductance amplifier for current monitor and load line of the
Northbridge VR.
Individual current sensing for Channel 1 of the Northbridge VR. If ISEN2_NB is tied to +5V, this pin cannot
be left open and must be tied to GND with a 10kΩ resistor. If ISEN1_NB is tied to +5V, the Northbridge
portion of the IC is shutdown.
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6377HRZ
ISL6377 HRZ
-10 to +100
48 Ld 6x6 QFN
L48.6x6B
ISL6377IRZ
ISL6377 IRZ
-40 to +85
48 Ld 6x6 QFN
L48.6x6B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6377. For more information on MSL please see tech brief TB363.
8
FN8336.0
August 6, 2012