ISL6377 Datasheet, PDF (33/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER
ISL6377 PIN SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are recommended to
connect this pad to the internal ground plane layers of the PCB
1
ISEN2_NB Each ISEN pin has a capacitor (C_isen) decoupling it to VSUMN_NB, then through another capacitor (C_{vsumn_nb}) to GND.
Place C_isen capacitors as close as possible to the controller and keep the following loops small:
1. ISEN1_NB pin to ISEN2_NB pin
2. Any ISENx_NB pin to GND
2
NTC_NB The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge thermal
throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard resistors in the
resistor network on this pin should be placed near the IC.
3
IMON_NB Place the IMON_NB resistor close to this pin and make keep a tight GND connection.
4
SVC Use good signal integrity practices and follow AMD recommendations.
5
VR_HOT_L Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended.
6
SVD Use good signal integrity practices and follow AMD recommendations.
7
VDDIO Use good signal integrity practices and follow AMD recommendations.
8
SVT Use good signal integrity practices and follow AMD recommendations.
9
ENABLE No special considerations.
10
PWROK Use good signal integrity practices and follow AMD recommendations.
11
NTC The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal throttling.
Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the resistor network on
this pin should be placed near the IC.
12
ISEN4
13
ISEN3 Each ISEN pin has a capacitor (C_isen) decoupling it to VSUMN and then through another capacitor (C_vsumn) to GND. Place
14
ISEN2
C_isen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
15
ISEN1 2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
ISEN 4
IS E N 3
Phase1
R isen
C isen
Phase1
R isen
L3
Ro
L3
Ro
C isen
V
Phase2
L2
R isen
Ro
IS E N 2
IS E N 1
GND
C isen
Phase3
R isen
Vsum n
C isen _{C vsum n}
L1
Ro
33
FN8336.0
August 6, 2012