ISL6377 Datasheet, PDF (20/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
TABLE 4. FCCM_NB RESISTOR SELECTION
RESISTOR VALUE
[kΩ]
SLEW RATE FOR CORE
AND NORTHBRIDGE
[mV/µs]
DriverX
PWM_Y
5.62
20
7.87
15
11.5
12.5
16.9
19.6
10
Core VR NB VR
20
Channel 3 Channel 1
24.9
15
34.0
12.5
41.2
10
52.3
20
73.2
15
95.3
12.5
121
10
NB VR Core VR
154
20
Channel 1 Channel 3
182
15
210
12.5
OPEN
10
VID-on-the-Fly Slew Rate Selection
The FCCM_NB resistor is also used to select the slew rate for VID
changes commanded by the processor. Once selected, the slew
rate is locked in during soft-start and is not adjustable during
operation. The lowest slew rate which can be selected is
10mV/µs which is above the minimum of 7.5mV/µs required by
the SVI2 specification. The slew rate selected sets the slew rate
for both Core and Northbridge VRs. The controller does not allow
for independent selection of slew rate.
CCM Switching Frequency
The Core and Northbridge VR switching frequency is set by the
programming resistors on COMP_NB and FCCM_NC. When the
ISL6377 is in continuous conduction mode (CCM), the switching
frequency is not absolutely constant due to the nature of the R³â„¢
modulator. As explained in “Multiphase R3™ Modulator” on
page 13, the effective switching frequency increases during load
insertion and decreases during load release to achieve fast
response. Thus, the switching frequency is relatively constant at
steady state. Variation is expected when the power stage
condition, such as input voltage, output voltage, load, etc.
changes. The variation is usually less than 10% and does not
have any significant effect on output voltage ripple magnitude.
Table 5 defines the switching frequency based on the resistor
values used to program the COMP_NB and FCCM_NB pins. Use
the previous tables related to COMP_NB and FCCM_NB to
determine the correct resistor value in these ranges to program
the desired output offset, Slew Rate and DriverX/PWM_Y
configuration.
TABLE 5. SWITCHING FREQUENCY SELECTION
FREQUENCY
[kHz]
COMP_NB
RANGE [kΩ]
FCCM_NB
RANGE [kΩ]
300
57.6 to OPEN
19.1 to 41.2
or
154 to OPEN
350
5.62 to 41.2
19.1 to 41.2
or
154 to OPEN
400
57.6 to OPEN
5.62 to 16.9
or
57.6 to 121
450
5.62 to 41.2
5.62 to 16.9
or
57.6 to 121
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes, and
shut down individual outputs.
AMD Serial VID Interface 2.0
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL6377. Once the PWROK
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL6377 uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
value. See Figure 11 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 6). Once the ENABLE input exceeds the rising
threshold, the ISL6377 decodes and locks the decoded value into
an on-board hold register.
TABLE 6. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
Once the programming pins are read, the internal DAC circuitry
begins to ramp Core and Northbridge VRs to the decoded
pre-PWROK Metal VID output level. The digital soft-start circuitry
ramps the internal reference to the target gradually at a fixed
rate of approximately 5mV/µs until the output voltage reaches
~250mV and then at the programmed slew rate. The controlled
ramp of all output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
PGOOD and PGOOD_NB outputs transition high, indicating both
output planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL6377 tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
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FN8336.0
August 6, 2012