ISL6377 Datasheet, PDF (14/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

V_CRM
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
COMP
VW
ISL6377
Figure 10 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6377 clamps
the ripple capacitor voltage V_CRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_CRS,
naturally stretching the switching period. The inductor current
triangles move farther apart, such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
VCRS
CCM/DCM BOUNDARY
VW
IL
VCRS
VW ^{LIGHT DCM}
VCRS1
VCRS3
VCRS2
FIGURE 8. R³â„¢ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
Diode Emulation and Period Stretching
The ISL6377 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As Figure 9
shows, when LGATE is on, the low-side MOSFET carries current,
creating negative voltage on the phase node due to the voltage
drop across the on-resistance. The ISL6377 monitors the current
by monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
PHASE
UGATE
LGATE
IL
FIGURE 9. DIODE EMULATION
If the load current is light enough, as Figure 9 shows, the inductor
current reaches and stays at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM, although the
controller is in DE mode.
IL
VCRS
DEEP DCM
VW
IL
FIGURE 10. PERIOD STRETCHING
Channel Configuration
Individual PWM channels of either VR can be disabled by
connecting the ISENx pin of the channel not required to +5V. For
example, placing the controller in a 3+1 configuration, as shown
in Figure 5, requires ISEN4 of the Core VR and ISEN2 of the
Northbridge VR to be tied to +5V. This disables Channel 4 of the
Core VR and Channel 2 of the Northbridge VR. ISEN1_NB must
be tied through a 10kΩ resistor to GND to prevent this pin from
pulling high and disabling the channel.
Connecting ISEN1 or ISEN1_NB to +5V will disable the
corresponding VR output. This feature allows debug of individual
VR outputs.
Power-On Reset
Before the controller has sufficient bias to guarantee proper
operation, the ISL6377 requires a +5V input supply tied to VDD
and VDDP to exceed the VDD rising power-on reset (POR)
threshold. Once this threshold is reached or exceeded, the
ISL6377 has enough bias to check the state of the SVI inputs
once ENABLE is taken high. Hysteresis between the rising and
the falling thresholds assure the ISL6377 does not inadvertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 10). Note that VIN must be
present for the controller to drive the output voltage.
14
FN8336.0
August 6, 2012