ISL6377 Datasheet, PDF (35/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER (Continued)
ISL6377 PIN SYMBOL
LAYOUT GUIDELINES
43
COMP_NB Place the compensation components in general proximity of the controller.
44
FB_NB
45
VSEN_NB Place the filter on this pin in close proximity to the controller for good coupling.
46
ISUMN_NB Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
47
ISUMP_NB _{Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.}
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on
a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
48
ISEN1_NB Each ISEN pin has a capacitor (C_isen) decoupling it to VSUMN_NB, then through another capacitor (C_{vsumn_nb}) to GND.
Place C_isen capacitors as close as possible to the controller and keep the following loops small:
1. ISEN1_NB pin to ISEN2_NB pin
2. Any ISENx_NB pin to GND
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
August 6, 2012
FN8336.0 Initial Release.
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35
FN8336.0
August 6, 2012