ISL6377 Datasheet, PDF (15/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
VDD
SVC
SVD
SVT
ENABLE
1
2
3
456
7
8
VOTF
TELEMETRY TELEMETRY
PWROK
V_CORE/ V_{CORE_NB}
PGOOD & PGOOD_NB
METAL_VID
V_SVI
Interval 1 to 2: ISL6377 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL6377 is prepared for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6377 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes.
Post 8: Telemetry is clocked out of the ISL6377.
FIGURE 11. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
Start-up Timing
With VDD above the POR threshold, the controller start-up
sequence begins when ENABLE exceeds the logic high threshold.
Figure 12 shows the typical soft-start timing of the Core and
Northbridge VRs. Once the controller registers ENABLE as a high,
the controller checks that state of a few programming pins
during the typical 8ms delay prior to beginning soft-starting the
Core and Northbridge outputs. The pre-PWROK Metal VID is read
from the state of the SVC and SVD pins and programs the DAC,
the programming resistors on COMP, COMP_NB, and FCCM_NB
are read to configure internal drivers, switching frequency, slew
rate, output offsets. These programming resistors are discussed
in subsequent sections. The ISL6377 use a digital soft-start to
ramp up the DAC to the Metal VID level programmed. The
soft-start slew rate is programmed by the FCCM_NB resistor
which is used to set the VID-on-the-Fly slew rate as well. See the
VID-on-the-Fly Slew Rate Selection section for more details on
selecting the FCCM_NB resistor. PGOOD is asserted high at the
end of the soft-start ramp.
VDD
ENABLE
DAC
PGOOD
PWROK
SLEW RATE
MetalVID _{VID COMMAND}
8ms
VOLTAGE
VIN
FIGURE 12. TYPICAL SOFT-START WAVEFORMS
Voltage Regulation and Load Line
Implementation
After the soft-start sequence, the ISL6377 regulates the output
voltages to the pre-PWROK metal VID programmed, see Table 6.
The ISL6377 controls the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.55V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
15
FN8336.0
August 6, 2012