ISL6377 Datasheet, PDF (17/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
The ISL6377 will adjust the phase pulse-width relative to the
other phases to make V_ISEN1 = V_ISEN2 = V_ISEN3 = V_ISEN4, thus to
achieve I_L1 = I_L2 = I_L3 = I_L4, when R_dcr1 = R_dcr2 = R_dcr3 = R_dcr4
and R_pcb1 = R_pcb2 = R_pcb3 = R_pcb4.
Using the same components for L1, L2, L3 and L4 provides a
good match of R_dcr1, R_dcr2, R_dcr3 and R_dcr4. Board layout
determines R_pcb1, R_pcb2, R_pcb3 and R_pcb4. It is recommended
to have a symmetrical layout for the power delivery path between
each inductor and the output voltage rail, such that
R_pcb1 = R_pcb2 = R_pcb3= R_pcb4.
IS E N 4
PHASE4 V4p
C isen
R isen
R isen
R isen
R isen
IS E N 3
IN T E R N A L
TO IC
IS E N 2
PHASE3 ^V3p
C isen
R isen
R isen
R isen
R isen
PHASE2 ^V2p
C isen
R isen
R isen
R isen
R isen
IS E N 1
PHASE1 ^V1p
C isen
R isen
R isen
R isen
R isen
L4
R dcr4
R pcb4
IL4
V4n
L3
R dcr3
R pcb3
IL3
V3n
L2
R dcr2
R pcb2
V_o
IL2
V2n
L1
R dcr1
R pcb1
IL1
V1n
FIGURE 15. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 14, asymmetric layout causes
different R_pcb1, R_pcb2, R_pcb3 and R_pcb4 values, thus creating a
current imbalance. Figure 15 shows a differential sensing current
balancing circuit recommended for ISL6377. The current sensing
traces should be routed to the inductor pads so they only pick up
the inductor DCR voltage. Each ISEN pin sees the average voltage
of three sources: its own, phase inductor phase-node pad, and
the other two phase inductor output side pads. Equations 10
through 13 give the ISEN pin voltages:
V_ISEN1 = V_1p + V_2n + V_3n + V_4n
(EQ. 10)
V_ISEN2 = V_1n + V_2p + V_3n + V_4n
(EQ. 11)
The ISL6377 will make V_ISEN1 = V_ISEN2 = V_ISEN3 = V_ISEN4 as
shown in Equations 14 and 16:
V_1p + V_2n + V_3n + V_4n = V_1n + V_2p + V_3n + V_4n
(EQ. 14)
V_1n + V_2p + V_3n + V_4n = V_1n + V_2n + V_3p + V_4n
V_1n + V_2n + V_3p + V_4n = V_1n + V_2n + V_3n + V_4p
(EQ. 15)
(EQ. 16)
Rewriting Equation 14 gives Equation 17:
V_1p – V_1n = V_2p – V_2n
(EQ. 17)
Rewriting Equation 15 gives Equation 18:
V_2p – V_2n = V_3p – V_3n
(EQ. 18)
Rewriting Equation 16 gives Equation 19:
V_3p – V_3n = V_4p – V_4n
(EQ. 19)
Combining Equations 17 through 19 gives:
V_1p – V_1n = V_2p – V_2n = V_3p – V_3n = V_4p – V_4n
Therefore:
R_dcr1 × I_L1 = R_dcr2 × I_L2 = R_dcr3 × I_L3 = R_dcr4 × I_L4
(EQ. 20)
(EQ. 21)
Current balancing (I_L1 = I_L2 = I_L3 = I_L4) is achieved when
R_dcr1 = R_dcr2 = R_dcr3 = R_dcr4. R_pcb1, R_pcb2, R_pcb3 and R_pcb4 do
not have any effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R³â„¢ modulator can naturally achieve excellent
current balancing during steady state and dynamic operations.
Figure 16 shows the current balancing performance of a three
phase evaluation board with load transient of 12A/51A at
different rep rates. The inductor currents follow the load current
dynamic change with the output capacitors supplying the
difference. The inductor currents can track the load current well
at a low repetition rate, but cannot keep up when the repetition
rate gets into the hundred-kHz range, where it is out of the
control loop bandwidth. The controller achieves excellent current
balancing in all cases installed.
V_ISEN3 = V_1n + V_2n + V_3p + V_4n
(EQ. 12)
V_ISEN4 = V_1n + V_2n + V_3n + V_4p
(EQ. 13)
17
FN8336.0
August 6, 2012