ISL6377 Datasheet, PDF (34/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
ISL6377 PIN
16
17
SYMBOL
ISUMP
ISUMN
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER (Continued)
LAYOUT GUIDELINES
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on
a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
18
VSEN Place the filter on these pins in close proximity to the controller for good coupling.
19
RTN
20
IMON Place the IMON resistor close to this pin and make keep a tight GND connection.
21
FB
Place the compensation components in general proximity of the controller.
22
COMP
23
PGOOD No special consideration.
24
BOOT1 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
25
UGATE1 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR Channel 1 high-
26
PHASE1 _{side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for better performance.}
27
LGATE1 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
28
PWM_Y No special considerations.
29
VDD A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
proximity to the pin with the filter resistor nearby the IC.
30
VDDP A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
proximity to the pin.
31
LGATE2 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
32
PHASE2 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR Channel 2 high-
33
UGATE2 _{side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for better performance.}
34
BOOT2 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
35
PWM4 No special considerations.
36
BOOTX Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
37
UGATEX These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
these signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side MOSFET source
38
PHASEX _{pin instead of a general connection to the PHASEX copper is recommended for better performance.}
39
LGATEX Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
40
PWM2_NB No special considerations.
41
FCCM_NB No special considerations.
42
PGOOD_NB No special consideration.
34
FN8336.0
August 6, 2012