ISL6377 Datasheet, PDF (32/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
The equivalent resistance at the typical thermal shutdown
threshold voltage of 0.58V required to shutdown both outputs is
defined in Equation 43.
0_-3---.0_--5_--μ-8_---A-V_{-- = 19.3kΩ}
(EQ. 43)
The NTC thermistor value correlates to the resistance change
between the warning and shutdown thresholds and the required
temperature change. If the warning level is designed to occur at a
board temperature of +100°C and the thermal shutdown level at
a board temperature of +105°C, then the resistance change of
the thermistor can be calculated. For example, a Panasonic NTC
thermistor with B = 4700 has a resistance ratio of 0.03939 of its
nominal value at +100°C and 0.03308 of its nominal value at
+105°C. Taking the required resistance change between the
thermal warning threshold and the shutdown threshold and
dividing it by the change in resistance ratio of the NTC thermistor
at the two temperatures of interest, the required resistance of
the NTC is defined in Equation 44.
(^--(-0^-2--.^{--10---.3--3--}9^--k-3^--Ω-9^{-----––-----}01^---.9^--0^-.--33^---3^-k---0^Ω---8^--)--) ^{= 317kΩ}
(EQ. 44)
The closest standard thermistor to the value calculated with
B = 4700 is 330kΩ. The NTC thermistor part number is
ERTJ0EV334J. The actual resistance change of this standard
thermistor value between the warning threshold and the
shutdown threshold is calculated in Equation 45.
(330kΩ ⋅ 0.03939) – (330kΩ ⋅ 0.03308) = 2.082kΩ
(EQ. 45)
Since the NTC thermistor resistance at +105°C is less than the
required resistance from Equation 43, additional resistance in
series with the thermistor is required to make up the difference.
A standard resistor, 1% tolerance, added in series with the
thermistor will increase the voltage seen at the NTC pin. The
additional resistance required is calculated in Equation 46.
19.3kΩ – 10.916kΩ = 8.384kΩ
(EQ. 46)
The closest, standard 1% tolerance resistor is 8.45kΩ.
The NTC thermistor is placed in a hot spot on the board, typically
near the upper MOSFET of Channel 1 of the respective output.
The standard resistor is placed next to the controller.
Layout Guidelines
PCB Layout Considerations
POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
COMPONENT PLACEMENT
There are two sets of critical components in a DC/DC converter;
the power components and the small signal components. The
power components are the most critical because they switch
large amounts of energy. The small signal components connect
to sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each
power train. Symmetrical layout allows heat to be dissipated
equally across all power trains. Keeping the distance between
the power train and the control IC short helps keep the gate drive
traces short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 31. TYPICAL POWER COMPONENT PLACEMENT
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible (see Figure 31). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target
(microprocessor), making use of the shortest connection paths to
any internal planes. Place the components in such a way that the
area under the IC has less noise traces with high dV/dt and di/dt,
such as gate signals and phase node signals.
Table 14 shows layout considerations for the ISL6377 controller
by pin.
32
FN8336.0
August 6, 2012