ISL6377 Datasheet, PDF (28/36 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL6377
ω_L
=
D_-----C_-----R_---
L
(EQ. 25)
ω_sns
=
---------------------------¹-----------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N----^u-------^m------
R_ntc
n
e
t
+
-^R----^s---^u---^m---
N
×
C_n
(EQ. 26)
where N is the number of phases.
Transfer function A_cs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R_ntc
value decrease as its temperature decreases. Proper selection of
R_sum, R_ntcs, R_p and R_ntc parameters ensures that V_Cn
represents the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the R_sum resistors form a voltage divider, V_cn is
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of V_cn to the inductor DCR voltage so the
droop circuit has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R_sum = 3.65kΩ, R_p = 11kΩ, R_ntcs = 2.61kΩ
and R_ntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current sensing network parameters to minimize engineering time.
V_Cn(s) also needs to represent real-time I_o(s) for the controller to
achieve good transient response. Transfer function A_cs(s) has a
pole w_sns and a zero w_L. One needs to match w_L and w_sns so
A_cs(s) is unity gain at all frequencies. By forcing w_L equal to w_sns
and solving for the solution, Equation 27 gives C_n value.
C_n
=
------------------------------^L--------------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N----^u-------^m------
R_n
t
c
ne
t
+
-^R----^s---^u---^m---
N
×
DCR
(EQ. 27)
For example, given N = 4, R_sum = 3.65kΩ, R_p = 11kΩ,
R_ntcs = 2.61kΩ, R_ntc = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
Equation 27 gives C_n = 0.518µF.
Assuming the compensator design is correct, Figure 21 shows the
expected load transient response waveforms if C_n is correctly
selected. When the load current I_core has a square change, the
output voltage V_core also has a square response.
If C_n value is too large or too small, V_Cn(s) does not accurately
represent real-time I_o(s) and worsens the transient response.
Figure 22 shows the load transient response when C_n is too
small. V_core sags excessively upon load insertion and may create
a system failure. Figure 23 shows the transient response when
C_n is too large. V_core is sluggish in drooping to its final value.
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
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FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
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FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO SMALL
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FIGURE 23. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO LARGE
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RING
BACK
FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM
28
FN8336.0
August 6, 2012