ISL70003ASEH Datasheet, PDF (7/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
Pin Descriptions (Continued)
PIN NUMBER PIN NAME ESD CIRCUIT
DESCRIPTION
7
AGND
1, 3
This pin is the analog ground associated with the internal analog control circuitry. Connect this pin
directly to the PCB ground plane.
8
DGND
2, 4
This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to
the PCB ground plane.
9
VREF_OUTS
4
This pin is the output of the internal linear regulator and the supply input to the internal reference
circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.
10
DVDD
6
This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to DVDD
should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.
11
VREFD
4
This pin is the output of the internal linear regulator and the bias supply input to the internal digital
control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
12
ENABLE
6
This pin is a logic-level enable input. Pulling this pin low powers down the device by placing it into a very
low power sleep mode.
13
RT/CT
6
A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8
as VIN varies.
14
FSEL
2
This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
15
SYNC
2
This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from
the internal oscillator or connected to an external clock for external frequency synchronization.
16
SS_CAP
2
This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set
the soft-start output ramp time in accordance with Equation 1:
t_SS = C_SS  V_REF  I_SS
(EQ. 1)
Where:
t_SS = soft-start output ramp time
C_SS = soft-start capacitance
V_REF = reference voltage (0.6V typical)
I_SS = soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor
should be 82nF to 8.2µF, inclusive.
17, 18, 19, 20, 21 GND
2
Connect these pin to the PCB ground plane.
22
PGOOD
6
This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when
the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage
from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.
23, 28, 32, 37,
38, 43, 44, 49,
53, 58
PVINx
7
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which should fall in the range of 3V to 13.2V. Bypass these
pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. When sinking
current or at a no load condition, the inductor valley current will be negative. During any time when the
inductor valley current is negative and the ISL70003A is exposed to a heavy ion environment, the abs
max PVIN voltage must be ≤13.7V.
29
SEL1
2
This pin is a logic-level disable (high) input working in conjunction with SEL2. These pins form a 2-bit
logic input that set the number of active power blocks. This allows the ISL70003ASEH current
capability to be tailored to the load current level the application requires and achieve the highest
possible efficiency.
30
SEL2
2
This pin is a logic-level disable input. Pulling this pin high inhibits pulses on the LXx outputs. See
description of Pin 29, SEL1, for more information.
31
DE
2
The DE pin enables or disables Diode Emulation. When it is HIGH, diode emulation is allowed.
Otherwise, continuous conduction mode is forced.
24, 27, 33, 36,
LXx
39, 42, 45, 48,
54, 57
These pins are the switch node connections to the internal power blocks and should be connected to
the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power
switches.
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7
FN8746.0
August 5, 2015