ISL70003ASEH Datasheet, PDF (22/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
EN pin may be tied to an input voltage >5V through a 50kΩ
resistor to minimize the current into the EN pin. The current
should not be allowed to exceed 160µA at any operating voltage.
5V _{INT. REG.}
POR
LOGIC
ENABLE
COMPARATOR
+
- ^VR
V_IN > 5.0V
PVINx
R1
51kΩ
EN
FIGURE 45. ENABLE TO V_IN FOR >5.0 INPUT VOLTAGE
Power-on Reset
After the EN input requirements are met, the ISL70003ASEH
remains in shutdown until the voltage at the POR pin rises above
its threshold. The POR circuitry prevents the controller from
attempting to soft-start before sufficient bias is present at the
PVINx pins.
As shown in Figure 46 on page 22, the POR circuit features a
comparator type input. The POR circuit allows the level of the
input voltage to precisely gate the turn-on/turn-off of the
regulator. An internal I_POR current sink with a typical value of
12µA is only active when the voltage on the POR pin is below the
enable threshold so it can pull the POR pin low. As V_IN rises, the
POR enable level is set by the resistor divider (R₁ and R₂) from
V_IN and the internal sink current source, I_POR.
V_R = 0.6V
I_POR = 12µA
C_POR = 10nF
5V _{INT. REG}
V_IN
PVINx
POR
LOGIC
POR
COMPARATOR
+
- ^VR
V_IN
R₁
POR
C_POR R₂
I_POR
Equation 2 defines the relationship between the resistor divider,
sink current and POR rising level (V_PORR).
V_PORR = V_R  1 + _R-^R----¹²- + I_POR  R₁
(EQ. 2)
Once the voltage at the POR pin reaches the enable threshold,
the I_POR current sink turns off.
With the part enabled and the I_POR current sink off, the falling level
(V_PORF) is set by the resistor divider network and is defined by
Equation 3.
V_PORF = V_R  1 + _R-^R----¹²-
(EQ. 3)
The difference between the POR rising and falling levels provides
adjustable hysteresis so that noise on V_IN does not interfere with
the enabling or disabling of the regulator.
Soft-start
The ISL70003ASEH soft-start function uses an internal current
source and an external capacitor to reduce stresses and surge
current during start-up.
Once the POR and enable circuits are satisfied, the regulator
waits 32 clock cycles and then initiates a soft-start. Figure 47
shows that the soft-start circuit clamps the error amplifier
reference voltage to the voltage on an external soft-start
capacitor connected to the SS pin. The soft-start capacitor is
charged by an internal I_SS current source. As the soft-start
capacitor is charged, the output voltage slowly ramps to the set
point determined by the reference voltage and the feedback
network. Once the voltage on the SS pin is equal to the internal
reference voltage, the soft-start interval is complete. Following
the soft-start interval is a delay to power good being signaled.
The soft-start output ramp interval is defined in Equation 4 and is
adjustable from approximately 2ms to 200ms. The value of the
soft-start capacitor, C_SS, should range from 82nF to 8.2µF,
inclusive. The peak inrush current can be computed from
Equation 5. The soft-start interval should be selected long
enough to insure that the peak inrush current plus the peak
output load current does not exceed the overcurrent trip level of
the regulator.
t_SS = C_SS  ^V----_I-^R-_S---^ES----^F-
(EQ. 4)
I_INRUSH = C_OUT  ^V----_t-^O-_S---^U-_S---^T--
(EQ. 5)
The soft-start capacitor is immediately discharged by a 3.0Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
FIGURE 46. POR CIRCUIT
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FN8746.0
August 5, 2015