ISL70003ASEH Datasheet, PDF (24/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
ϭϬ
ϵ
LOAD CURRENT, 5A/DIV
Ï´
ϳ
0A
ϲ
ϱ
OUTPUT VOLTAGE, 1V/DIV
Ï°
ϯ
0V
Ï®
Ï­
SOFT-START VOLTAGE, 1V/DIV
Ϭ
0V
5ms/DIV
FIGURE 49. OVERCURRENT BEHAVIOR IN HICCUP MODE
After the regulator shuts down, it enters a delay interval, allowing
the device to cool. The delay interval is approximately equal to
512 clock cycles plus 1 soft-start intervals. The overcurrent
counter is reset entering the delay interval. The protection logic
initiates a normal soft-start once the delay interval ends. If the
output successfully soft starts, the power-good signal goes high
and normal operation continues. If overcurrent conditions
continue to exist during the soft-start interval, the overcurrent
counter must overflow before the regulator shutdowns the output
again. This hiccup mode continues indefinitely until the output
soft starts successfully (see Figure 49).
Load Regulation
The ISL70003ASEH is a metal only revision of the ISL70003SEH
specifically to improve load regulation across the wider 9A output
current rating. Although the load regulation is now improved by an
order of magnitude there are performance generalities to be
aware of; higher temperature, lower PVIN and higher VOUT/PVIN
ratio all yield tighter load regulation performance. The switching
frequency has no deterministic effect, producing differences 1
order of magnitude less than the other condition considerations.
Figure 2 on page 2 and Figures 24, 25, 26, 27 on page 18
illustrate performance trends for a sampling of these conditions.
Application Information
Voltage Feed-forward
Feed-forward is used to maintain a constant modulator gain and
achieve optimum loop response over a wide input voltage range.
A resistor from PVINx to RTCT and a capacitor from RTCT to
PGNDx are used to adjust the amplitude of the sawtooth ramp
proportional to the input voltage. The capacitor value must be
chosen so that it is large enough for mitigation of single event
transients but low enough for the internal MOSFET device to pull
the pin to ground. The following table gives the recommended
values for R_T and C_T for a given switching frequency. These
values will achieve a constant modulator gain across the
complete input voltage range.
FSEL STATE
0
1
f_SW (kHz)
500
300
R_T (kΩ)
22
36
C_T (pF)
370
370
MODULATOR
GAIN (TYP)
5
4.8
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Switching Frequency Selection
There are a number of variables to consider when choosing the
switching frequency. A high switching frequency increases the
switching losses but may lead to a decrease in output filter size. A
lower switching frequency may increase efficiency but may lead to
more output voltage ripple and increased output filter size.
On the ISL70003ASEH, the switching frequency is determined by
the state of the TTL/CMOS compatible FSEL pin. A logic low will
set the regulator to operate with a 500kHz switching frequency,
while a logic high sets a 300kHz switching frequency.
Synchronization
The ISL70003ASEH, can be synchronized to an external clock
with a frequency range of 500kHz ±15% or 300kHz ±15%,
depending on the state of the FSEL pin.
The SYNC pin accepts the external clock signal and the regulator
will be synchronized in phase with the external clock. During
start-up the regulator will use its internal oscillator to regulate
the output voltage. Once soft-start is complete and PGOOD is
released, the regulator will synchronize to the external clock
signal. This feature allows the ISL70003ASEH regulator to be the
power source to the external components that will be providing
the external clock without the requirement that a signal must be
present at the SYNC pin before start-up.
Output Voltage Selection
ERROR
AMPLIFIER
-
+
LXx ^LO
V_OUT
C_O
R₁
FB
NI
R₄
V_REF
REF
C_REF
FIGURE 50. OUTPUT VOLTAGE SELECTION
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the reference voltage. The reference voltage and the
noninverting input to the error amplifier are not internally
connected, therefore, for standalone applications the REF pin
must be tied to the NI pin (see Figure 50). The REF pin should be
bypassed to AGND with a 220nF ceramic capacitor to mitigate
SEE. It should be noted that no current (sourcing or sinking) is
available from the REF pin.
The output voltage programming resistor, R₄, will depend on the
value chosen for the feedback resistor R₁ and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 5kΩ and 25kΩ.
If the output voltage desired is 0.6V, then R₄ is left unpopulated.
R₄ = -V---R-_O-----^1U-----_T-^-----_–--⁰----0^.---⁶--.--6-^V----V---
(EQ. 6)
FN8746.0
August 5, 2015