ISL70003ASEH Datasheet, PDF (6/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

Pin Configuration
BOTTOM SIDE DETAIL
FOR PIN 1 LOCATION
ISL70003ASEH
ISL70003ASEH
(64 LD CQFP)
TOP VIEW
1 (NI) NI
FB
VERR
POR_VIN
VREFA
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
ENABLE
RT/CT
FSEL
SYNC
SS_CAP
1 ⁶⁴
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
2
47
3
46
4
45
5
44
6
(Note 3)
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
HEATSINK OUTLINE *
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LX3
PGND3
PGND4
LX4
PVIN4
PVIN5
LX5
PGND5
PGND6
LX6
PVIN6
PVIN7
LX7
PGND7
PGND8
LX8
NOTE:
3. The ESD triangular mark is indicative of pin #1 location. It is part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
* Indicates heatsink package R64.C
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
PIN NAME ESD CIRCUIT
DESCRIPTION
NI
1
This pin is the noninverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
FB
1
This pin is the inverting input to the internal error amplifier. An external type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
VERR
1
This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
POR_VIN
1
This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
VREFA
3
This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
AVDD
5
This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
Submit Document Feedback
6
FN8746.0
August 5, 2015