ISL70003ASEH Datasheet, PDF (27/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
The added power source has a cluster of requirements that
should be observed and considered. Due to the reduced
differential thresholds of DDR memory, the termination power
supply voltage, V_TT, closely tracks V_DDQ/2 voltage.
Another very important feature of the termination power supply
is the capability to operate at equal efficiency in sourcing and
sinking modes. The V_TT supply regulates the output voltage with
the same degree of precision when current is flowing from the
supply to the load, and when the current is diverted back from
the load into the power supply.
The ISL70003ASEH regulator possesses several important
enhancements that allow reconfiguration for DDR memory
applications. Two ISL70003ASEH ICs will provide all three
voltages required in a DDR memory compliant system.
DDR Configuration
V_DDQ
ISL70003ASEH 1/2
R_T1
FB
R_{B1 NI}
ERROR
- ^AMPLIFIER
+
V_DDQ
R_T1
REF
V_REF
V_IN
PVIN_x
LX_x ^LO
PGND_x
V_DDQ
C_O1
R_B1
V_TT
NI
R_T2
FB
R_B2
B⁺
V_DDQ
B^-
R
R
ISL70003ASEH 2/2
ERROR
+ ^AMPLIFIER
-
BUFFER
+ ^AMPLIFIER
-
OUTB
V_IN
PVIN_x
LX_x ^LO
PGND_x
V_TT
C_O2
V_REF
C_O3
FIGURE 55. SIMPLIFIED DDR APPLICATION SCHEMATIC
In the DDR application presented in Figure 55, an independent
architecture is implemented to generate the voltages needed for
DDR memory applications. Consequently, both V_DDQ and V_TT are
derived independently from the main power source. The first
regulator supplies the 2.5V for the V_DDQ voltage. The output
voltage is set by external dividers R_T1 and R_B1. The second
regulator generates the V_TT rail typically = V_DDQ/2. The resistor
divider network R_T2 and R_B2 are used to set the output voltage to
1.25V. The V_DDQ rail has an additional voltage divider network
consisting of R_T1 and R_B1, the midpoint is connected to the
noninverting input pin of the V_TT regulator’s error amplifier (NI),
effectively providing a tracking function for the V_TT voltage.
The noninverting input of the buffer amplifier is connected to the
center point of the external R/R divider from the VDDQ output.
The output of the buffer is tied back to the inverting input for
unity gain configuration. The buffer output voltage serves as a
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1.25V reference (VREF) for the DDR memory devices. Sourcing
capability of the buffer amplifier is 10mA typical (20mA max)
and needs a minimum of 1µF load capacitance for stability.
Diode emulation mode of operation must be disabled on the V_TT
regulator to allow sinking capability. In the event both channels
are enabled simultaneously, the soft-start capacitor on the VDDQ
regulator should be two to three times larger than the soft-start
capacitor on the V_TT regulator. This allows the VDDQ regulator
voltage to be the lowest input into the error amplifier of the V_TT
regulator and dominate the soft-start ramp. However, if the V_TT
regulator is enabled later than the VDDQ, the soft-start capacitor
can be any value based on design goals.
Each regulator has its own fault protections and must be
individually configured. All the sink current on the V_TT regulator is
provided by the VDDQ rail, the overcurrent protection on the
VDDQ rail will limit the amount of current that the V_TT rail will
sink.
When sinking current or at a no load condition, the inductor
valley current is negative, see Figure 36. During any time when
the inductor valley current is negative and the ISL70003A is
exposed to a heavy ion environment the abs max PVIN voltage
must be ≤13.7V, see Note 5 on page 11.
SEL1 and SEL2 may be tied together and used to place the V_TT
regulator in sleep mode, common to DDR applications. The
outputs will be tri-stated, however the buffer amplifier is still
active and the VREF voltage will be present even if the V_TT is in
sleep mode. When SEL1 and SEL2 are asserted low, the V_TT
regulator will ramp-up the voltage. The ramp is controlled and
timing is based on soft-start capacitor value.
Refer to Figure 5 on page 10 for complete DDR power solution
typical application circuit schematic.
Operational Envelope
The ISL70003ASEH, is rated for operation across a PVIN of 3V to
13.2V, for a V_OUT of 0.6V to ~11.9V, and an output current up to
9A, with a 500kHz switching frequency and to a +125°C die
temperature. While rated to these conditions, operation is not
simultaneously all inclusive as there are combinations of these
conditions, particularly at the extremes, where it will not operate,
thus defining a conditional operation envelope.
Figures 13 and 18 show the reduced output current capability for
the PVIN = 3.3V, V_OUT = 2.5V condition illustrating one corner of
the envelope where the ratio of V_OUT to PVIN is too high in
combination with the temperature and current extremes. The
converter runs into regulation issues with a 500kHz switching
frequency due to inadequate off time being realized under these
conditions. Another conditional operation corner, being the
situation where the ratio of V_OUT to PVIN is too low and the result
is current limiting. In both of these extreme conditions the
maximum output current capability is reduced and output
accuracy is compromised.
These graphs are to be considered illustrative of the operation
envelope and not guidance. Users must characterize and
evaluate their circuit performance to their satisfaction when
approaching the extreme conditions of voltage, current and
temperature.
FN8746.0
August 5, 2015