ISL70003ASEH Datasheet, PDF (25/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
Setting the Overcurrent Protection Level
The ISL70003ASEH features dual redundancy in the overcurrent
detection circuitry, which helps avoid false overcurrent triggering
due to single event effects. Two external resistors from pins
OCSETA and OCSETB to AGND set the level of the overcurrent
protection (OCP) trip point. The OCP circuit senses the peak
current across a pilot device not the average current so it is
important to determine the overcurrent trip point (I_OCP) greater
than the maximum output continuous current (I_MAX) plus half
the maximum inductor ripple current (ΔI).
Use Equation 7 to determine the peak-to-peak inductor ripple
current:
I = ^V-----^I-_f-^N-_S----–_W----^V---_--^O--_L--^U----^T--  D
(EQ. 7)
Where f_SW is the switching frequency, L is the output inductor
value and D is duty cycle. Once an I_OCP value is chosen that
satisfies Equation 8:
I_OCP  I_MAX + ^--₂---^I
(EQ. 8)
Equation 9 may be used to determine the value of R_OCSETA and
R_OCSETB with all 10 power blocks active.
R_{OCSETA B} = ³--_I--_O⁶---⁰-_C--²--_P--⁴--
(EQ. 9)
The minimum value for R_OCSET(A,B) is 2.87kΩ, which is
equivalent to a 12.5A I_OCP level.
Disabling the Power Blocks
The ISL70003ASEH offers two TTL/CMOS compatible power
block select pins, SEL1 and SEL2, which form a 2-bit logic input
that are used to turn off the internal power blocks. Depending on
the state of the SEL1 and SEL2 pins, the ISL70003ASEH can
operate with 2, 4 or 10 power blocks on or have all the outputs in
a tri-state mode. This allows the designer to reduce switching
losses in low current applications, where all power blocks are not
needed to supply the load current. Table 1 compares the logic
state of SEL1 and SEL2 with the current capability of the
regulator and the number of active LXx pins.
SEL2
STATE
0
TABLE 1. LOGIC STATE COMPARISON
SEL1
STATE
ACTIVE LXx PINS
LOAD CAPABILITY
(T_J = +125°C)
0
All
9A
0
1
5, 6, 7, 8
3.6A
1
0
5, 6
1.8A
1
1
None
N/A
With both SEL pins in a logic high state, the ISL70003ASEH is in
a low power sleep mode where all outputs are tri-stated. Once
the logic activates the power blocks, the regulator ramps the
output voltage to its set value within a soft-start interval,
however, the device no longer goes through the preinitialization
phase.
Transitions between the number of active LXx pins through the
use of SEL1 and SEL2 should not be done while the part is
operating. On the fly transitions will cause glitches on the output
voltage which may exceed transient requirements. It is
recommended to place the ISL70003ASEH in standby mode, by
pulling SEL1 and SEL2 HIGH, then change the number of active
LXx pins.
The overcurrent trip point scales depending on the number of
active power blocks. Equation 10 may be used to determine the
value of R_OCSETA and R_OCSETB when less than 10 power blocks
are active:
R_{OCSETA B} = ³----⁶---⁰-_I--_O²----^._C-⁴----_P-^-----^N---
(EQ. 10)
Where N is the number of active power block phases.
IMON Current Sense Output
The ISL70003ASEH provides a current monitor function through
IMON. Current monitoring informs designers if downstream loads
are operating as expected. It is also useful in the prototype and
debug phase of the design and during normal operation to
measure the overall performance of a system. The IMON pin
outputs a high speed analog current source that is proportional
to the sensed peak current through the ISL70003ASEH. In typical
applications, a resistor R_IMON is connected to the IMON pin to
convert the sensed current to voltage, V_IMON, which is
proportional to the peak current, as shown in Equation 11:
V_IMON = 100  10^–6  ^I--^S----^A----^M-----^P----^L---^E--_N---^-----^R-----^I-^M-----^O-----^N--
(EQ. 11)
Where V_IMON is the voltage at the IMON pin, R_IMON is the resistor
between the IMON pin and AGND, I_SAMPLE is the current through
the converter at the time IMON samples the current, and N is the
number of active power blocks. I_SAMPLE may be calculated from
Equation 12.
I_SAMPLE = I_LOAD + ^--₂---^I – _{}I  -^t-^S----^A----^M--_---₁^P----^L-–--^E--_D---^--_---^f--^S----^W---_
(EQ. 12)
Where t_SAMPLE is the time it takes the IMON circuitry to sample
the current (300ns, max.), I_LOAD is the load current and ΔI is the
inductor peak-to-peak ripple current as calculated in Equation 7.
A small capacitor should be placed between the IMON pin and
AGND to reduce the noise impact and mitigate single event
transients. If this pin is not used, it is best connected to VREFA. It
is also acceptable to tie to GND through a resistor.
Figures 51 and 52 show the response of the IMON current
monitor due to a load step with a R_IMON = 10kΩ and 100pF
ceramic capacitor in parallel.
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FN8746.0
August 5, 2015