ISL70003ASEH Datasheet, PDF (29/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a
direct consequence of the amount of capacitance on the output.
V_OUT
ΔV_HUMP
ΔV_ESR
ΔV_SAG
ΔV_ESL
I_OUT
I_TRAN
FIGURE 57. TYPICAL TRANSIENT RESPONSE
During the removal of the same output load, the energy stored in
the inductor is dumped into the output capacitors. This energy
dumping creates a temporary hump in the output voltage. This
hump, as with the sag, can be attributed to the total amount of
capacitance on the output. Figure 57 shows a typical response to
a load transient.
The amplitudes of the different types of voltage excursions can
be approximated using Equation 15.
V_ESR = ESR ² I_tran
V_ESL
=
ESL ² ^d------I--t---^r---^a----ⁿ---
dt
V_SAG = _C------O------_U---L---_T-^O-----²-^U----_--^T--V----²-_I--_N---I--^t--_–-^r---^a---V--ⁿ--_O--²-----_U-----_T-----_-
V_HUMP
=
-L----^O------^U------^T-------²-----I--^t---^r---^a-----ⁿ----²---
C_OUT ² V_OUT
(EQ. 15)
Where I_tran = Output Load Current Transient and C_OUT = Total
Output Capacitance
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the ESL are
typically the major contributing factors in determining the output
capacitance. The number of output capacitors can be
determined by using Equation 16, which relates the ESR and ESL
of the capacitors to the transient load step and the voltage limit
(ΔVo).
Number of Capacitors = --E----------S----------L------------²----d-------d---t--------I----^t------^r------^a---------^{n---------+-------E-----S-----R-------²------I--t}---^r---^a-----ⁿ--
V_o
(EQ. 16)
If ΔV_SAG and/or ΔV_HUMP are found to be too large for the output
voltage limits, then the amount of capacitance may need to be
increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
The ESL of the capacitors, which is an important parameter in
the previous equations, is not usually listed in databooks.
Practically, it can be approximated using Equation 17 if an
Impedance vs Frequency curve is given for a specific capacitor:
ESL = -------------------------1----------------------------
C2 ²  ² f_res²
(EQ. 17)
Where: f_res is the frequency where the lowest impedance is
achieved (resonant frequency).
The ESL of the capacitors becomes a concern when designing
circuits that supply power to loads with high rates of change in
the current.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high-frequency decoupling and bulk capacitors to supply the
current needed each time the upper MOSFET turns on. Place the
small ceramic capacitors physically close to the MOSFETs and
between the drain of the upper MOSFET and the source of the
lower MOSFET.
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors may be
closely approximated using Equation 18:
V-----_{O-----U----T-}
V_IN
x



I_O
U
TM
A
2
X
x


1
–
-V--V--^O---_I--^UN----^T-_
+
---1-----
12
x



-V----L^I--^N---_x----^–-f---_O--V---_S--^O--_C--^U----^T-
x
V-----_{O-----U----T-}
V_{IN }
2_


(EQ. 18)
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the capacitor
surge current rating. These capacitors must be capable of
handling the surge current at power-up. Some capacitor series
available from reputable manufacturers are surge current tested.
Feedback Compensation
Figure 58 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage (V_OUT)
is regulated to the reference voltage level. The error amplifier
output (V_EA) is compared with the oscillator (OSC) triangular
wave to provide a pulse-width modulated (PWM) wave with an
amplitude of V_IN at the PHASE node. The PWM wave is smoothed
by the output filter (L_O and C_O).
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FN8746.0
August 5, 2015