ISL70003ASEH Datasheet, PDF (26/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
VIMON VOLTAGE
200mV/DIV
INDUCTOR
CURRENT
2A/DIV
TIME (5µs/DIV)
FIGURE 51. IMON RESPONSE TO 6A LOAD STEP
VIMON VOLTAGE
200mV/DIV
INDUCTOR
CURRENT
2A/DIV
Diode Emulation
Diode Emulation (DE) allows for higher converter efficiency under
light load situations. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and does not
allow reverse current, emulating a diode. As shown in Figure 54,
when the LGATE signal is HIGH, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. When the DE pin is pulled
HIGH, the ISL70003ASEH will be in diode emulation mode and
detect the zero current crossing of the inductor current and turn
off the lower MOSFET to prevent the inductor current from
reversing direction and creating unnecessary power loss. This
ensures that discontinuous conduction mode (DCM) is achieved.
Since diode emulation prevents the low-side MOSFET from
sinking current, no negative spike at the output is generated
during prebiased startup when DE mode is active.
After a significantly fast load release transient, diode emulation
will not allow the converter to bring the output voltage back down
following the hump created by the inductor energy dump into the
output capacitor bank. The ISL70003ASEH overcomes this issue
by monitoring the output of the error amplifier and allowing the
low-side MOSFET to turn on and sink the necessary current
needed to properly regulate the output voltage. The same
mechanism allows the converter to properly regulate the output
voltage when starting into a prebiased condition where the
prebias level is greater than the desired output voltage.
TIME (5µs/DIV)
FIGURE 52. IMON RESPONSE TO 6A LOAD RELEASE
Although the IMON output reflects the peak current sensed, it
can be also used to approximate the DC output current with a
more accurate approximation at higher current levels and lower
PVIN voltage. Figure 53 shows a graph normalized to 100µA of
IMON current to 1A of output current across a 10kΩ resistor.
2.0
1.8
1.6
13.2_VIN_5V_OUT
1.4
5_VIN_1.5V_OUT
3.0_VIN_1.5V_OUT
1.2
1.0
0.8
1
2
3
4
5
6
7
8
9
OUTPUT CURRENT (A)
FIGURE 53. IMON TO DC I_OUT
It is important to note that if the on time of the lower NMOS FET
is shorter than the IMON current sense time (300ns max), the
IMON output is tri-stated after 4 consecutive failed sense
occurrences.
LXx
UGATE
LGATE
I_L
FIGURE 54. DIODE EMULATION
The DE pin is not intended to actively change states while the
regulator is operating. If any part of the inductor current is below
zero and the DE pin changes state there will be a glitch on the
output voltage. However, if the state of the DE pin changes state
when the inductor current is positive, no change in the operation
of the regulator will be seen.
DDR Application
High throughput Double Data Rate (DDR) memory ICs are
replacing traditional memory ICs in space applications. A novel
feature associated with this type of memory are the referencing
and data bus termination techniques. These techniques employ
a reference voltage, V_REF, that tracks the center point of V_DDQ
and V_SS voltages, and an additional V_TT power source where all
terminating resistors are connected. Despite the additional
power source, the overall memory power consumption is reduced
compared to traditional termination.
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FN8746.0
August 5, 2015