ISL70003ASEH Datasheet, PDF(30/36 Page) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

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ISL70003ASEH Datasheet, PDF (30/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

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ISL70003ASEH

OSC

PWM

COMPARATOR

Î VOSC

DRIVER

VIN

PHASE CO

VOUT

ZFB

VEA

ZIN

ERROR REFERENCE

AMP

ESR

(PARASITIC)

DETAILED COMPENSATION COMPONENTS

ZFB

VOUT

ZIN

C3 R3

VERR

REFERENCE

VOUT

0.6

Â¥

ï¦

ï§

ï¨

RR-----14--ï¸ï·ï¶

FIGURE 58. VOLTAGE-MODE BUCK CONVERTER COMPENSATION

The modulator transfer function is the small-signal transfer

function of VOUT/VEA. This function is dominated by a DC Gain and

the output filter (LO and CO), with a double pole break frequency at

fLC and a zero at fESR. The DC gain of the modulator is simply the

input voltage (VIN) divided by the peak-to-peak oscillator voltage

ÎVOSC. The ISL70003ASEH incorporates a feed-forward loop that

accounts for changes in the input voltage. This maintains a

constant modulator gain of 5, typical.

Modulator Break Frequency Equations

LC=

--------------------1---------------------

2ï° x LO x CO

fESR= -2---ï°------x-----E----S--1---R------x-----C-----O--

(EQ. 19)

The compensation network consists of the error amplifier and

the impedance networks ZIN and ZFB. The goal of the

compensation network is to provide a closed loop transfer

function with the highest 0dB crossing frequency (f0dB) and

adequate phase margin. Phase margin is the difference between

the closed loop phase at f0dB and 180Â°.

100

fZ1 fZ2 fP1 fP2

OPEN LOOP

ERROR AMP GAIN

40 20LOG

20 (R2/R1)

20LOG

(VIN/DVOSC)

-20

MODULATOR

GAIN

-40

-60 10

100

fLC

fESR

10k 100k

COMPENSATION

GAIN

CLOSED LOOP

GAIN

1M 10M

FREQUENCY (Hz)

FIGURE 59. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Equation 20 relates the compensation networkâs poles, zeros

and gain to the components (R1 , R2, R3, C1 , C2 and C3) in

Figure 58. Use these guidelines for locating the poles and zeros

of the compensation network:

1. Pick gain (R2/R1) for desired converter bandwidth.

2. Place 1st zero below filterâs double pole (~75% FLC).

3. Place 2nd zero at filterâs double pole.

4. Place 1st pole at the ESR zero.

5. Place 2nd pole at half the switching frequency.

6. Check gain against error amplifierâs open-loop gain.

7. Estimate phase margin - repeat if necessary.

Compensation Break Frequency Equations

fZ1 = -2---ï°------x-----R--1--2-----x------C----1-

fP1

---------------------------1-----------------------------

2ï°

ï¦

ï§

ï¨

C-C----1-1----+x-----CC----2-2-ï¸ï·ï¶

fP2 = -2---ï°------x-----R--1--3------x-----C----3-

(EQ. 20)

Figure 59 shows an asymptotic plot of the DC/DC converterâs

gain vs frequency. The actual modulator gain has a high gain

peak due to the high Q factor of the output filter and is not shown

in Figure 59. Using the guidelines provided should give a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

compensation gain at fP2 with the capabilities of the error

amplifier. The closed loop gain is constructed on the graph of

Figure 59 by adding the modulator gain (in dB) to the

compensation gain (in dB). This is equivalent to multiplying the

modulator transfer function to the compensation transfer

function and plotting the gain. The compensation gain uses

external impedance networks ZFB and ZIN to provide a stable,

high bandwidth (BW) overall loop. A stable control loop has a

gain crossing with -20dB/decade slope and a phase margin

greater than +45Â°. Include worst case component variations

when determining phase margin. A more detailed explanation of

voltage mode control of a buck regulator can be found in Tech

Brief TB417, entitled âDesigning Stable Compensation Networks

for Single Phase Voltage Mode Buck Regulatorsâ.

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FN8746.0

August 5, 2015

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