ISL70003ASEH Datasheet, PDF (23/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

ISL70003ASEH
V_REF = 0.6V
I_SS = 23µA
R_D = 2.2Ω
FB
PWM
LOGIC
ERROR
AMPLIFIER
-
+
+ _{VREF RD}
SS
NI
I_SS
V_OUT
R_T
R_B
C_SS
V_REF
REF
C_REF
FIGURE 47. SOFT-START CIRCUIT
Power-good
A power-good indicator is the final step of initialization. After a
successful soft-start, the PGOOD pin releases and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The PGOOD pin is an open-drain logic output and can be pulled
up to any voltage from 0V to 13.2V. The pull-up resistor should
have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should
be bypassed to DGND with a 10nF ceramic capacitor to mitigate
SEE.
Fault Monitoring and Protection
The ISL70003ASEH actively monitors the output voltage and
current to detect fault conditions. Fault conditions trigger
protective measures to prevent damage to the regulator and the
external load device. One common power-good indication signal
is provided for linking to external system monitors. The
schematic in Figure 48 on page 23 outlines the interaction
between the fault monitors and the power-good signal.
Undervoltage and Overvoltage Monitor
The power-good pin (PGOOD) is an open-drain logic output which
indicates that the converter is operating properly and the output
voltage is within a set window. The undervoltage (UV) and
overvoltage (OV) comparators create the output voltage window.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on page 13. If the feedback voltage
exceeds the typical rising limit of 111% of the reference voltage,
the PGOOD pin pulls low. The PGOOD pin continues to pull low
until the feedback voltage falls to a typical of 107.5% of the
reference voltage. If the feedback voltage drops below a typical
of 89% of the reference voltage, the PGOOD pin pulls low. The
PGOOD pin continues to pull low until the feedback voltage rises
to a typical 92.5% of the reference voltage. The PGOOD pin then
releases and signals the return of the output voltage within the
power-good window.
0.666V
+
OV
-
PGOOD
+
UV
-
FB
0.534V
COUNTER/
POR/ ON-OFF
CONTROL
I_SEN
-
+
UVP
OCP
+
OCSETB
-
0.45V
I_SEN
-
OCP
+
OCSETA
FIGURE 48. POWER-GOOD AND OC PROTECTION CIRCUITRY
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that is a
fixed percentage of the reference voltage, typically 75%. Once the
comparator trips, indicating a valid undervoltage condition, an
undervoltage counter increments. The counter is reset if the
feedback voltage rises back above the undervoltage threshold plus
a specified amount of hysteresis outlined in the “Electrical
Specifications” table on page 13. If there are 4 consecutive
undervoltage detections the counter will overflow and the
undervoltage protection logic shuts down the regulator, pulling
PGOOD low.
After the regulator shuts down, it enters a delay interval,
approximately equivalent to 512 clock cycles plus 1 soft-start
intervals, allowing the device to cool. The undervoltage counter is
reset entering the delay interval. The protection logic initiates a
normal soft-start once the delay interval ends. If the output
successfully soft starts, the power-good signal goes high and normal
operation continues. If undervoltage conditions continue to exist
during the soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This hiccup mode
continues indefinitely until the output soft starts successfully.
Overcurrent Protection
A pilot device integrated into the PMOS transistor of Power Blocks
5 and 6 sample the current each cycle. This current feedback is
scaled and compared to an overcurrent threshold based on the
resistor value tied from pins OCSETA and OCSETB to AGND.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will increment. However, if the
sampled current falls below the threshold the counter is reset. If
there are 4 sequential OC fault detections, the counter will
overflow and the regulator will be shut down under an
overcurrent fault condition, pulling PGOOD low.
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FN8746.0
August 5, 2015