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ISL70003ASEH Datasheet, PDF (1/36 Pages) Intersil Corporation – Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator | |||
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DATASHEET
Radiation and SEE Tolerant 3V to 13.2V, 9A Buck
Regulator
ISL70003ASEH
The ISL70003ASEH is an improved version of the ISL70003SEH
regulator with both tighter load regulation (<0.3% typical) and a
higher output current rating of 9A. Operating over an input voltage
range of 3.0V to 13.2V, with integrated low rDS(ON) MOSFETs
makes this monolithic solution highly efficient. Also, a tightly
regulated output voltage is possible, which is externally
adjustable from 0.6V to ~90% of the input voltage. Continuous
output load current capability is 9A for TJ â¤+125°C and 6A for
TJ â¤+150°C.
The ISL70003ASEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance.
The device features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003ASEH also supports DDR applications and contains a
buffer amplifier for generating the VREF voltage.
High integration, best in class radiation performance and a
feature filled design make the ISL70003ASEH an ideal choice
to power many of todays small form factor applications.
All existing ISL70003SEH supporting collateral is relevant to
the ISL70003ASEH and can be used as such.
Applications
⢠FPGA, CPLD, DSP, CPU core and I/O supply voltages
⢠DDR memory supply voltages
⢠Low-voltage, high-density distributed power systems
Related Literature
⢠AN1897, âISL70003SEHEV1Z Evaluation Boardâ
⢠AN1915, âISL70003SEH iSim:PE Modelâ
⢠TR009, âSingle Event Effects (SEE) Testing of the
ISL70003ASEH POL BUCK Regulatorâ
⢠AN1924, âTotal Dose Testing of the ISL70003SEH Radiation
Hardened Point Of Load Regulatorâ
⢠TB502, âHigh Power ISL70003ASEH High Temperature
Operating Life (HTOL) and Overcurrent Abuseâ
⢠UG046, âISL70003ASEHEV2Z Evaluation Board User Guideâ
Features
⢠Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
⢠±1% reference voltage over line, temperature and radiation
⢠Integrated MOSFETs 31mΩï PFET/21mΩ NFET
- 95% peak efficiency
⢠Externally adjustable loop compensation
⢠Supports DDR applications (VTT tracks VDDQ/2)
- Buffer amplifier for generating VREF voltage
- 3A current sinking capability
⢠Grounded lid eliminates charge build up
⢠IMON pin for output current monitoring
⢠Adjustable analog soft-start
⢠Diode emulation for increased efficiency at light loads
⢠500kHz or 300kHz operating frequency
⢠Monotonic start-up into prebiased load
⢠Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
⢠Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
⢠SEE hardness
- SEB and SEL LETTH . . . . . . . . . . . . . . . . 86.4MeVâ¢cm2/mg
- SET at LET 86.4MeVâ¢cm2/mg . . . . . . . . . . . < ±3% ÎVOUT
- SEFI LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeVâ¢cm2/mg
⢠Electrically screened to DLA SMD 5962-14203
0.3
0.2
-55°C
0.1
+25°C
+125°C
0.0
-0.1
+85°C
-0.2
-0.3
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (A)
FIGURE 1. TYPICAL LOAD REGULATION, VIN = 12V, VOUT = 3.3V,
fSW = 500kHz
August 5, 2015
1
FN8746.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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