ISL35822 Datasheet, PDF (64/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
Table 115. MDIO INTERFACE TIMING (FROM IEEE802.3AE) (SEE Figure 15 TO Figure 17)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
T_MDCD
ISL35822 MDIO out delay from MDC
0
5.0
300
ns
T_MDS
Setup from MDIO in to MDC
10
1.5
ns
T_MDH
T_MDC
T_MDV
T_Update
Hold from MDC to MDIO in
Clock Period MDC ⁽¹⁾
MDC Clock HI or LO time⁽¹⁾
Delay from last data bit to register update⁽²⁾
10
1.5
100
400
20
160
2
ns
ns
ns
T_MDC
C_MD
Input Capacitance
10
pF
Note (1): The ISL35822 will accept a much higher MDC clock rate and shorter HI and LO times than the IEEE802.3 specification (section 22.2.2.11) requires. Such a
faster clock may not be acceptable to other devices on the interface.
Note (2): The ISL35822 MDIO registers will not be written until two MDC clocks have occurred after the frame end. These will normally count toward the minimum
preamble before the next frame, except in the case of writing a RESET into [1,3,4].0.15, see Figure 17.
SYMBOL
T_RSTBIT
T_MDRST
Table 116. RESET AND MDIO TIMING (SEE Figure 17)
PARAMETER
MIN
TYP
Reset bit Active width
2
Delay from Reset bit to first active preamble count
240
256
MAX
282
UNITS
T_MDC
T_REFCLK
Table 117. RESET AND I²C SERIAL INTERFACE TIMING (SEE Figure 18 AND Figure 24)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
T_RESET
T_WAIT
T_TRAIN
T_{CLAH_L}
T_{SCL_DAV}
RSTN Active width
Delay from RSTN to I²C SCL Start
I²C ‘training’ (external reset)
Period of I²C SCL Clock Line (400kHz)
Setup from I²C SDA Data Valid to SCL edge
10
10
30
2.5
100
µs
ms
T_{CLAH_L}
µs⁽¹⁾
ns
T_{SDA_CLV}
Setup, Hold from SDA for START, STOP
600
ns
C_I2C
Input Capacitance
10
pF
Note (1): Assuming RFCP-N clock is 156.25MHz, and register bits 1.8005.6:4 set for 400kHz (Table 20). SCL clock period scales with reference clock frequency. Also,
per the I²C specification, the SCL ‘High’ time is stretched by the time taken for SCL to go high after the ISL35822 releases it, to allow an I²C slave to demand
additional time. Any RC delays on the SCL line will add to the SCL ‘High’ time, in increments of approximately 100ns.
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