ISL35822 Datasheet, PDF (50/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
Table 85. PHY XS PRE-EMPHASIS CONTROL
BIT
4.49157.15:12
NAME
Reserved
MDIO REGISTER ADDRESS = 4.49157 (4.C005’h)
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
4.49157.11:9
4.49157.8:6
PRE_EMP Lane 3
PRE_EMP Lane 2
See Table 86 for 0’h
settings
0’h
R/W
Configure the level of PHY XS pre-emphasis
(nominal levels indicated)
4.49157.5:3
PRE_EMP Lane 1
0’h
4.49157.2:0
PRE_EMP Lane 0
0’h
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
ADDRESS
4.C005’h
BITS 2:0
000
Table 86. PHY XS XAUI PRE-EMPHASIS CONTROL SETTINGS
PRE-EMPHASIS ⁽¹⁾
(802.3ak) =
(1-V_LOW/V_HI)
PRE-EMPHASIS VALUE = ADDRESS 4.C005’h
(V_HI/ V_LOW)-1
BITS 2:0
PRE-EMPHASIS
(802.3ak) =
(1-V_LOW/V_HI)
0
0
100
0.50
001
0.17
0.20
101
0.53
010
0.28
0.39
110
0.57
011
0.44
0.79
111
0.60
Note (1): See Note (2) to Table 42 for a note about the equations and symbols used here.
PRE-EMPHASIS
VALUE =
(V_HI/ V_LOW)-1
1.00
1.28
1.33
1.50
Table 87. PHY XS EQUALIZATION CONTROL
MDIO REGISTER ADDRESS = 4.49158 (4.C006’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
4.49158.15:14
Reserved
4.49158.3:0
PHY XS
EQ_COEFF
0’h = no boost in equalizer. 0’h
F’h = boost is maximum
R/W
Configuration of the PHY XS equalizer
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 88. PHY XS RECEIVE PATH TEST AND STATUS FLAGS
MDIO REGISTER ADDRESS = 4.49159 (4.C007’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
4.49159.15:12
Test Flags
0’h
ROLH Special test use only
4.49159.11
4.49159.10
4.49159.9
EFIFO_3
EFIFO_2
EFIFO_1
1 = EFIFO error in Lane 0’b
0 = no EFIFO error in
Lane
0’b
0’b
ROLH
PHY XS Elasticity FIFO Overflow/Underflow
Error Detection⁽¹⁾
4.49159.8
EFIFO_0
0’b
4.49159.7
4.49159.6
4.49159.5
Code_3
Code_2
Code_1
1 = 10b/8b Code error in 0’b
Lane
0 = no 10b/8b Code error
0’b
0’b
ROLH
PHY XS 10b/8b Decoder Code Violation
Detection⁽¹⁾
4.49159.4
4.49159.3
4.49159.2
Code_0
BIST_ERR_3
BIST_ERR_2
0’b
1 = BIST error in lane 0’b
0 = No BIST error in lane _0’b
ROLH
Lane by lane BIST error checker indicator^{(1) (2)}
4.49159.1
BIST_ERR_1
0’b
4.49159.0
BIST_ERR_0
0’b
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
register 1.9004’h (see Table 28)
Note (2): See also error counters in registers 3.C00D:E’h (Table 73)
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