ISL35822 Datasheet, PDF (21/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
IEEE PMA/PMD REGISTERS (1.0 TO 1.15/1.000F’H)
Table 5. IEEE PMA/PMD CONTROL 1 REGISTER
MDIO REGISTER ADDRESS = 1.0 (1.0000’h)
BIT(S)
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.0.15
3.0.15
4.0.15
Reset
1 = reset
0’b
0 = reset done, normal
operation
R/W SC Writing 1 to this bit will reset the whole chip,
including the MDIO registers. ⁽¹⁾
1.0.14
Reserved
0’b
1.0.13
Speed Select
1 = 10Gbps
1’b
RO
1 = bits 5:2 select speed
1.0.12
Reserved
0’b
1.0.11
LOPOWER
0 = Normal Power
0’b
R/W
No Low Power Mode, writes ignored
1.0.10:7 Reserved
0’h
1.0.6
Speed Select
1 = 10Gbps
1’b
RO
1 = bits 5:2 select speed
1.0.5:2
Speed Select
0000 = 10Gbps
0’h
RO
Operates at 10Gbps
1.0.1
Reserved
0’b
1.0.0
PMA Loopback 1 = Enable loopback
0’b
R/W
Enable serial loop back mode on all four lanes,
0 = Normal operation
XAUI in to XAUI out.
Note (1): After this RESET bit is written, the ISL35822 will not begin counting PREAMBLE bits immediately. See Figure 17 for details.
Table 6. IEEE PMA/PMD STATUS 1 REGISTER
MDIO REGISTER ADDRESS = 1.1 (1.0001’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.1.15:8 Reserved
00’h
1.1.7
Local Fault
1 = PMA Local Fault
0’b
RO
Derived from Register 1.8.11:10
1.1.6:3
1.1.2
Reserved
Rx Link Up
1 = PMA Rx Link Up
0 = PMA/D Rx Link Down
0’h
1’b ⁽¹⁾
RO LL⁽¹⁾
‘Up’ means CX4/LX4 signal level is OK, and the
PLL locked
1.1.1
LoPwrAble
Low Power Ability
0’b
RO
Device does not support a low power mode
1.1.0
Reserved
0’b
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
BIT
1.4.15:3
3.4.15:2
4.4.15:1
1.4.2:1
3.4.1
1.4.0
3.4.0
4.4.0
Table 7. IEEE PMA/PMD, PCS, PHY XS, SPEED ABILITY REGISTER
MDIO REGISTER ADDRESSES = 1.4, 3.4 & 4.4 ([1,3,4].0004’h)
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
Reserved for future
speeds
000’h
10PASS-T2/
2BASE-TL
10GbpsAble
EFM Ability
10Gbps Ablility
00’b
RO
Device cannot operate @ 2BASE-TL or 10PASS-
T2
1’b
RO
Device Able to operate @ 10Gbps
21