ISL35822 Datasheet, PDF (23/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
Table 10. IEEE PMA/PMD STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER (Continued)
MDIO REGISTER ADDRESSES = 1.8 (1.0008’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.8.5
10GBASE-ER
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-ER
1.8.4
10GBASE-LX4
1 = can perform
1’b
RO
Device can be 10GBASE-LX4
1.8.3
10GBASE-SW
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-SW
1.8.2
10GBASE-LW
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-LW
1.8.1
10GBASE-EW
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-EW
1.8.0
PMA Loopback
1 = can perform
1’b
RO
Device can perform PMA loopback
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28).
Note (2): The source of ‘Loss of Signal’ depends on the LX4/CX4 select LX4_MODE pin (see register 1.10, 12, note (1) below).
Table 11. IEEE TRANSMIT DISABLE REGISTER
MDIO REGISTER ADDRESS = 1.9 (1.0009’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.9.15:5
1.9.4
1.9.3
1.9.2
1.9.1
Reserved
PMD Dis 3
PMD Dis 2
PMD Dis 1
PMD Dis 0
Disable TX on Lane 3⁽¹⁾
Disable TX on Lane 2⁽¹⁾
Disable TX on Lane 1⁽¹⁾
Disable TX on Lane 0⁽¹⁾
0’b
R/W
1 = Disable PMD Transmit on respective Lane⁽¹⁾
0’b
R/W
0 = Enable PMD Transmit on respective Lane
(unless TXON/OFF pin is Low)
0’b
R/W
0’b
R/W
1.9.0
PMD Dis All
Disable TX on all 4 Lanes
0’b
R/W
Note (1): In CX4 mode the TCXnP/N pin outputs will be disabled; in LX4 Mode only TX_ENA[n] pin is disabled.
Table 12. IEEE PMD SIGNAL DETECT REGISTER
MDIO REGISTER ADDRESS = 1.10 (1.000A’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.10.15:5
1.10.4
1.10.3
1.10.2
1.10.1
1.10.0
Reserved
PMD Rx Ln 3
PMD Rx Ln 2
PMD Rx Ln 1
PMD Rx Ln 0
PMD Rx Glob
PMD Signal Det’d
PMD Signal Det’d
PMD Signal Det’d
PMD Signal Det’d
PMD Signal Det’d
1’b⁽¹⁾
1’b⁽¹⁾
1’b⁽¹⁾
1’b⁽¹⁾
1’b⁽¹⁾
RO
1 = PMD Signal Detected on respective Lane
(Global, all Lanes)
RO
0 = PMD Signal not detected on respective Lane
RO
(Global, any
Lane)
RO
RO
Note (1): These bits reflect the OPRLOS[3:0] pins (Table 99) in LX4 mode, or the CX4 SIGNAL_DETECT function in CX4 mode, depending on the LX4_MODE select pin.
Table 13. IEEE EXTENDED PMA/PMD CAPABILITY REGISTER⁽¹⁾
MDIO Register Addresses = 1.11 (1.000B’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.11.15:1
1.11.0⁽¹⁾
Reserved
10GBASE-CX4
1 = can perform
0000’h
1’b
RO
RO
Device can be 10GBASE-CX4
Note (1): These values reflect the IEEE 802.3ak 10GBASE-CX4 specification.
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